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| PRELIMINARY TECHNICAL DATA a Preliminary Technical Data Communications System Supervisory/Sequencing Circuit ADM1060 ADM1060 TABLE OF CONTENTS Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ADM1060 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ADM1060 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Powering the ADM1060 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Programmable Supply Fault Detectors (SFD's) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SFD Comparator Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bipolar SFD's . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SFD Fault Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Glitch Filtering on the SFD's . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Programming the SFD's on the SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SFD Register Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SFD Register Bitmaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Bipolar Supply Fail Detect (BSnSFD) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 High Voltage Supply Fault Detect (HVSFD) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Positive Voltage Supply Fault Detect (PSnSFD) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Watchdog Fault Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 General Purpose Inputs (GPI's) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Logic State of the GPI's (and other Logic Inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Programmable Logic Block Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PLBA Register Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PLBA Register Bitmaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Programmable Delay Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Programmable Driver Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Fault/Status Reporting on the ADM1060 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Fault Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Configuuration Download at Power- Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Updating the Configuration of the ADM1060 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Internal Registers of the ADM1060 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 General SMBus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 SMBus Protocols for RAM and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ADM1060 Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ADM1060 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Applications Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 REV. PrJ 11/02 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002 PRELIMINARY TECHNICAL DATA ADM1060 FEATURES Faults detected on 7 independent supplies * 1 High Voltage supply (up to 14.4V) * 4 Positive Voltage Only Supplies (up to 6V) * 2 Positive/Negative Voltage supplies (up to +6V OR down to -6V) Watchdog Detector Input- Timeout delay programmable from 200ms to 12.8sec 4 General Purpose Logic Inputs Programmable Logic Block- combinatorial and sequencing logic control of all inputs and outputs 9 Programmable Output Drivers * Open Collector (external resistor required) * Open Collector with internal pull-up to VDD * Fast Internal pull-up to VDD * Open Collector with internal pull-up to VPn * Fast Internal pull-up to VPn * Internally charge pumped high drive (for use with external N- channel FETS- PDO's 1 to 4 only) EEPROM- 512 Bytes Industry Standard 2- Wire Bus Interface (SMBus) Guaranteed PDO Low with VPn, VH=1V APPLICATIONS Other inputs to the ADM1060 include a Watchdog Detector (WDI) and 4 General Purpose Inputs (GPIn). The Watchdog Detector can be used to monitor a processor clock. If the clock does not toggle (transition from low to high or from high to low) within a programmable timeout period (up to 18 sec.), a fail flag will assert. The 4 General Purpose inputs can be configured as logic buffers or to detect positive/negative edges and to generate a logic pulse or level from those edges. Thus, the user can input control signals from other parts of their system (eg RESET or POWER_GOOD) to gate the sequencing of the supplies supervised by the ADM1060. The ADM1060 features 9 Programmable Driver Outputs (PDO's). All 9 outputs can be configured to be logic outputs, which can provide multiple functions for the end user such as RESET generation, POWER_GOOD status, enabling of LDO's, Watchdog Timeout assertion etc. PDO's 1- 4 have the added feature of being able to provide an internally charge pumped high voltage for use as the gate drive of an external N- Channel FET which could be placed in the path of one of the supplies being supervised. All of the inputs and outputs described above are controlled by the Programmable Logic Block Array. This is the logic core of the ADM1060. It is comprised of 9 macrocells, one for each PDO. These macrocells are essentially just wide AND gates. Any/all of the inputs can be used as an input to these macrocells. The output of a macrocell can also be used as an input to any macrocell other than itself (an input to itself would result in a noterminating loop). The PLBA outputs control the PDO's of the ADM1060 via delay blocks, where a delay of between 0 and 500ms can be programmed on the rising and/ or the falling edge of the data. This results in a very flexible sequencing ability. Thus, for instance, PDO1 can be programmed so that it will not assert until, say, VP2, VP3and VP4 supplies are in tolerance, VB1 and VH have been in tolerance for 200mS, and PDO7 has already been asserted. A simple sequencing operation would be to daisy chain each PLB output into the input of the next PLB such that PDO9 doesn't assert until PDO8 asserts, which in turn doesn't assert until PDO7 asserts etc. All of the functional capability described here is programmable through the industry standard 2 wire bus (SMBus) provided. Device settings can be written to EEPROM memory for automatic programming of the device on power-up. The EEPROM is organised in 512 bytes, half of which are used to program all of the functions on the ADM1060. The other 256 bytes of EEPROM are for general purpose system use (eg) date codes, system ID etc. Read/write access to this is also via the 2 wire interface. In addition, each output state can be directly overdriven from the serial interface, allowing a further level of control (eg) a system controlled soft powerdown. Central Office Systems Servers Infrastructure Network Boards High density, multi- voltage system cards GENERAL DESCRIPTION The ADM1060 is a programmable supervisory/sequencing device which offers a single chip solution for multiple power supply fault detection and sequencing in communications systems. In central office, servers and other infrastructure systems, a common backplane dc supply is reduced to multiple board supplies using dc/dc converters. These multiple supplies are used to power different sections of the board (eg) 3.3V Logic circuits, 5V logic circuits, DSP core and I/O circuits etc. There is usually a requirement that certain sections power up before others (eg) a DSP core to power up before the DSP I/O or vice versa. This is in order to avoid damage, miscommunication or latch- up. The ADM1060 facilitates this, providing supply fault detection and sequencing/combinatorial logic for up to 7 independent supplies. The 7 Supply Fault Detectors consist of one high voltage detector (up to +14.4V), two bipolar voltage detectors (up to +6V OR down to -6V) and 4 positive low voltage detectors (up to +6V). All of the detectors can be programmed to detect undervoltage, overvoltage or out- of window (undervoltage OR overvoltage) conditions. The inputs to these Supply Fault Detectors are via the VH pin (High Voltage), VBn pins (positive OR negative) and VPn pins (Positive only) pins respectively. Either the VH supply or one of the VPn supplies is used to power the ADM1060 (whichever is highest). This ensures that, in the event of a supply failure, the ADM1060 is kept alive for as long as possible, thus enabling a reliable fault flag to be asserted and the system to be powered down in an ordered fashion. -2- REV. PrJ 11/02 PRELIMINARY TECHNICAL DATA ADM1060 PROGRAMMABLE DELAY BLOCKS PROGRAMMABLE LOGIC BLOCK ARRAY (PLBA) HIGH SUPPLY(14.4v) FAULT DETECTOR PLB MACROCELL 1 PDB1 PROGRAMMABLE DRIVER OUPUTS PDO1 15 PDO1 TRISE TFALL VH 8 PDB2 PDO2 VP1 VP2 VP3 VP4 9 POSITIVE SUPPLY FAULT DETECTOR 1 TRISE TFALL 16 PDO2 PDB3 PLB MACROCELL 2 TRISE TFALL 10 11 12 PDO3 17 PDO3 PLB MACROCELL 3 POSITIVE SUPPLY FAULT DETECTOR 4 PLB MACROCELL4 TRISE TFALL PDB4 PDO4 18 PDO4 VB1 13 BIPOLAR SUPPLY FAULT DETECTOR 1 PDB5 PLB MACROCELL 5 TRISE TFALL PDO5 19 PDO5 VB2 14 BIPOLAR SUPPLY FAULT DETECTOR 2 PLB MACROCELL 6 PDB6 PDO6 GPI1 GPI2 GPI3 GPI4 WDI 28 27 26 25 24 WATCHDOG FAULT DETECTOR 20 PDO6 PLB MACROCELL 7 TRISE TFALL PDB7 INPUT LOGIC SIGNAL CONDITION PLB MACROCELL 8 TRISE TFALL PDO7 21 PDO7 PLB MACROCELL 9 PDB8 PDO8 TRISE TFALL 22 PDO8 GND PDB9 6 VREF TRISE TFALL PDO9 1 0 0 K H z C L O C K EEPROM 23 PDO9 Internal 5.5V supply VCCP 7 REGULATED 5.5V SUPPLY CHARGE PUMP Data, Address and Write Enable Buses to store control information local to functions S M B U S D A T A VDD ARBITRATOR SMBus INTERFACE DEVICE CONTROLLER 5 4 3 2 1 VDDCAP SDA SCL A1 ADM1060 FUNCTIONAL BLOCK DIAGRAM REV. PrJ 11/02 -3- A0 PRELIMINARY TECHNICAL DATA ADM1060-SPECIFICATIONS (VH=4.5V to 14.4V, VPn = 3.0V to 6.0V 2, TA = -40oC to 85oC, unless otherwise noted.) Parameter POWER SUPPLY ARBITRATION VDDCAP Min 2.7 2.7 4.75 4.75 POWER SUPPLY Supply Current, IDD 3 5.1 5.1 Typ Max Units V V V mA Test Conditions/Comments Any VPn>=3.0V VH>=4.5V Any VPn=6.0V VH=14.4V VDDCAP=4.75V, no PDO FET Drivers on, no loaded PDO pullups to VDDCAP VDDCAP=4.75V, all PDO FET Drivers on (loaded with 1 A), no PDO pullups to VDDCAP Max. additional load that can be drawn from PDO pullups to VDDCAP 5 mA Additional current available from VDDCAP 1 mA SUPPLY FAULT DETECTORS VH Input Input Impedance Threshold Ranges Mid Range Programming Step High Range Programming Step VPn Inputs Input Impedance Threshold Ranges Ultra Low Range Programming Step Low Range Programming Step Mid Range Programming Step VBn Inputs Input Impedance 52 2 Size 4.8 Size 37.6 52 0.6 Size 1 Size 2 Size 15.6 190 52 30 7.8 6 4.7 3 1.8 15.6 14.4 6 k V mV V mV k V mV V mV V mV k k k From VH to GND From VPn to GND From VBn to 2.25V (Internal Ref.) From VBn to GND (positive mode) From VBn to GND (negative mode) Threshold Ranges Negative Mode: Mid Range Programming Step Size Positive Mode: Low Range Programming Step Size Mid Range Programming Step Size Absolute Accuracy Absolute AccuracyCalibrated Voltage Thresholds4 Threshold Programming Resolution Digital Glitch Filter NOTES 1 2 3 4 -6 15.6 1 7.8 2 15.6 -2 V mV V mV V mV % % 8 TA=0oC to 85oC, Threshold Voltage>0.9V Bits See figure 3. 8 timeout options between 0 and 100 s 3 6 2.5 1.0 0 100 s These are target specifications and At least one VPn must be >=3.0V Logic inputs will accept input high Calibrated Voltage Thresholds are subject to change. if used as supply. VH must be >=4.5V if used as supply. voltages up to 5.5V even when device is operating at supply voltages below 5V. set at Production. -4- REV.PrJ11/02 PRELIMINARY TECHNICAL DATA ADM1060-SPECIFICATIONS1 (VH=4.5V to 14.4V, VPn = 3.0V to 6.0V2, TA = -40oC to 85oC, unless otherwise noted.) Parameter PROGRAMMABLE DRIVER OUTPUTS High Voltage (Charge Pump) Mode (PDO's 1 to 4) Output Impedance, ROUT V OH I OUTAVG Standard (Digital Output) Mode (PDO's 1 to 9) V OH Min Typ Max Units Test Conditions/Comments 10.5 10 440 12.5 12 20 14 k V V A IOH= 0 I OH =1 A 2V V V V V V V mA k mA VOL I SINK R PULLUPI SOURCE (VPn) 0.4 1.2 2.0 20 Weak Pull-up 20 2 Tristate Output Leakage Current DIGITAL INPUTS (GPI 1-4,WDI,A0,A1) Input High Voltage, VIH Input Low Voltage, VIL Input High Current, I IH Input Low Current, IIL Input Capacitance Programmable Pulldown Current, I PULLDOWN SERIAL BUS DIGITAL INPUTS (SDA,SCL) Input High Voltage, VIH Input Low Voltage, VIL Output Low Voltage, VOL PROGRAMMABLE DELAY BLOCK Timeout WATCHDOG TIMER INPUT Timeout SERIAL BUS TIMING Clock Frequency, fSCLK Glitch Immunity, tSW Bus Free Time, tBUF Start Setup Time, tSU;STA Start Hold Time, tHD;STA SCL Low Time, tLOW SCL High Time, tHIGH SCL, SDA Rise Time, tr SCL, SDA Fall Time, tf Data Setup Time, tSU;DAT Data Hold Time, tHD;DAT NOTES 1 2 3 4 10 A 2.0 0.8 -1 1 TBD 10 V V A A pF A Max. V IN=5.5V Max. V IN=5.5V VIN = 5.5V VIN = 0 If known logic state required 2.0 0.8 0.4 0 500 V V V ms IOUT = -3.0mA 16 programmable options on both rising and falling edge 8 programmable timeout options See See See See See See See See See See See Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 8c 8c 8c 8c 8c 8c 8c 8c 8c 8c 8c 0 12.8 400 50 s KHz ns s s s s s ns s ns ns 4.7 4.7 4 4.7 4 1000 300 250 300 These are target specifications and subject to change. At least one supply connected to VH or VPn must be >=3.0V Logic inputs will accept input high voltages up to 5.5V even when device is operating at supply voltages below 5V. Timing specifications are tested at logic levels of V IL = 0.8V for a falling edge and VIH = 2.2V for a rising edge. REV.PrJ 11/02 -5- PRELIMINARY TECHNICAL DATA ADM1060 PIN FUNCTION DESCRIPTION Pin 1 2 3 4 5 6 7 Mnemonic A0 A1 SDA SCL VDDCAP GND VCCP Function Logic input. Controls the 7th bit (LSB) of the 7 bit Serial Bus Address. Logic input. Controls the 6th bit of the 7 bit Serial Bus Address. Serial Bus data I/O pin. Open- Drain output. Open- Drain Serial Bus Clock pin. VDD bypass capacitor pin. Requires 2.2k pullup resistor Requires 2.2k pullup resistor A capacitor from this pin to GND stabilises the VDD Arbitrator. 0.1 F is recommended for this function. Ground. Connect to common of power supplies. Reservoir Capacitor for Central Charge Pump. This charge pump powers all of the internal circuits of the ADM1060 and provides the first stage in the tripler circuits used to produce 12V of gate drive on PDO's 1- 4. High Voltage Supply Input. 2 input ranges. A supply of between 2V and 6V or between 4.8V and 14.4V can be applied to this pin. The VDD arbitrator will select this supply to power the ADM1060 if it is the highest supply supervised. Positive Only Supply Inputs. 2 input ranges. A supply of between 1V and 3V or between 2V and 6V can be applied to this pin. The VDD arbitrator will select one of these supplies to power the ADM1060 if it is the highest supply supervised. Bipolar Supply Inputs. 2 modes. 2 input ranges in positive mode. 1 input range in negative mode. A supply of between -6V and -2V can be applied to this pin when set in negative mode. A supply of between 1V and 3V or between 2V and 6V can be applied to this pin when set in positive mode. Programmable Driver Output pin. All 9 can be programmed as logic outputs with multiple pull-up options to VDD or VPn. PDO's 1 to 4 can also provide a charge-pump generated gate drive for external N- Channel FET Watchdog Input. Used to monitor a processor clock and asserts a fault condition if the clock fails to transition from low-to-high or high-to-low within a programmed timeout period (up to 18sec). General Purpose Logic Input. TTL compatible Logic. Can be used as, say, a Manual a Chip Enable pin or as an input for a control logic signal which may be critical to the power up/down sequence of the supplies under control. A0 A1 SDA SCL VDDCAP GND VCCP VH VP1 1 2 3 4 28 GPI1 27 GPI2 26 GPI3 25 GPI4 8 VH 9-12 VP1-4 13-14 VB1-2 15-23 PDO_1-9 24 WDI 25-28 Reset, GPI_4-1 ABSOLUTE MAXIMUM RATINGS* Voltage on VH Pin . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V Voltage on VP Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V Voltage on VB Pins . . . . . . . . . . . . . . . . . . . . . -7 V to +7V Voltage on A0,A1 . . . . . . . . . . . . . . -0.3V to (V CC+0.3V) Voltage on Any Other Input . . . . . . . . . . . . . . -0.3V to 6.5V Input Current at any pin . . . . . . . . . . . . . . . . . . . . . . 5mA Package Input Current . . . . . . . . . . . . . . . . . . . . . . 20mA Maximum Junction Temperature (TJ max) . . . . . . . 150 C Storage Temperature Range . . . . . . . . . -65C to +150C Lead Temperature, Soldering Vapor Phase 60 sec . . . . . . . . . . . . . . . . . . . . . . . +215C ESD Rating all pins . . . . . . . . . . . . . . . . . . . . . . . . 2000 V *Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ADM1060 5 6 7 8 9 VP2 10 FT RA UT DO PIN 17 24 WDI 23 PDO9 22 PDO8 21 PDO7 20 PDO6 19 PDO5 VP3 11 VP4 12 VB1 13 VB2 14 18 PDO4 PDO3 16 PDO2 15 PDO1 ADM1060 PIN CONFIGURATION ORDERING GUIDE Model ADM1060ARU Temperature Range -40C to +85C Package Description 28-PinTSSOP Package Option RU-28 THERMAL CHARACTERISTICS 28-Pin TSSOP Package: JA = 98C/Watt -6- REV. PrJ 11/02 PRELIMINARY TECHNICAL DATA ADM1060 INPUTS ADM1060 INPUTS POWERING THE ADM1060 The ADM1060 is powered from the highest voltage input on either the Positive Only supply inputs (VPn) or the High Voltage supply input (VH). The same pins are used for supply fault detection (discussed below) . A VDD Arbitrator on the device chooses which supply to use. The arbitrator can be considered to be diode OR'ing the positive supplies together (as shown in figure 1). In addition to this, the diodes are supplemented with switches in a synchronous rectifier manner, to minimise voltage loss. This loss can be reduced to ~0.2V, resulting in the ability to power the ADM1060 from a supply as low as 3.0V. Note that the supply on the VBn pins cannot be used to power the device, even if the input on these pins is positive. Also, the minimum supply of 3.0V must appear on one of the VPn pins in order to power up the ADM1060 correctly. A supply of no less than 4.5V can be used on VH. This is because there is no synchronous rectifier circuit on the VH pin, resulting in a voltage drop of ~1.5V across the diode of the VDD Arbitrator. An external cap to GND is required to decouple the onchip supply from noise. This cap should be connected to the VDDCAP pin, as shown in figure 1. The cap has another use during "brown outs" (momentary loss of power). Under these conditions, where the input supply, VPn, dips transiently below VDD, the synchronous rectifier switch immediately turns off so that it doesn't pull VDD down. The VDD cap can then act like a reservoir and keep the chip active until the next highest supply takes over the powering of the device. 0.1 F is recommended for this function. Note that in the case where there are 2 or more supplies within 100mV of each other, the supply which takes control of VDD first will keep control (e.g) if VP1 is connected to a 3.3V supply, then VDD will power up to approximately 3.1V through VP1. If VP2 is then connected to another 3.3V supply, VP1 will still power the device, unless VP2 goes 100mV higher than VP1. VH ADM1060 PROGRAMMABLE SUPPLY FAULT DETECTORS (SFD'S) The ADM1060 has seven programmable Supply Fault Detectors, 1 high voltage detector (2V to 14.4V), 2 bipolar detectors (2V to 6V, -2V to -6V) and 4 Positive only voltage detectors (0.6V to 6V). Inputs are applied to these detectors via the VH (High Voltage Supply input) pin, VBn (Bipolar Supply input) pins and VPn (Positive Only input) pins respectively. The SFD's detect a fault condition on any of these input supplies. A fault is defined as Undervoltage (where the supply drops below a preprogrammed level), Overvoltage (where the supply rises above a preprogrammed level) or Out-of-Window (where the supply deviates outside either the programmed overvoltage OR undervoltage threshold). Only one fault type can be selected at a time. An Undervoltage fault is detected by comparing the input supply to a programmed reference (the undervoltage threshold). If the input voltage drops below the undervoltage threshold the output of the comparator goes high, asserting a fault. The undervoltage threshold is programmed using an 8 bit DAC. On a given range, the UV threshold can be set with a resolution of:Step Size = Threshold Range/255 An Overvoltage (OV) fault is detected in exactly the same way, using a second comparator and DAC to program the reference. All thresholds are programmed using 8 bit registers, one register each for the 7 UV thresholds and 1 each for the 7 OV thresholds. The UV or OV threshold programmed by the user is given by:VT= VR x N + VB 255 where:VT = Desired Threshold Voltage (UV or OV) VR= Threshold Voltage Range N = Decimalized version of 8 bit code VB = Bottom of Threshold Range This results in the code for a given threshold being given by:N=255 x (VT- VB)/VR VP1 VP2 VP3 VP4 Limit current VDDCAP pin surge to VDDI/ decoupling cap Off -chip decoupling capacitor Thus, for example, if the user wishes to set a 5V OV threshold on VP1, the code to be programmed in the PS1OVTH register (discussed later) would be given by:N=255 x (5-2)/4 VDDI Figure 1. VDD Arbitrator Operation REV. PrJ 11/02 -7- PRELIMINARY TECHNICAL DATA ADM1060 Thus, N=192 (11000000 or C0H) The available threshold ranges, and the resolution they are programmed to are shown in table 1. Note that the low end of the detection range is fixed to 33.33% of the top of the range. Note also, that for a given SFD, the ranges overlap (eg) VH goes from 2V to 6V then from 4.8V to 14.4V. This is to provide better threshold setting resolution as supplies decrease in value. Input Name VH VBn Voltage Ranges 4.8V to 14.4V 2V to 6V 2V to 6V 1V to 3V -6V to -2V 2V to 6V 1V to 3V 0.6V to 1.8V Resolution 37.6mV 15.6mV 15.6mV (Pos. Mode) 7.8mV " 15.6mV (Neg. Mode) 15.6mV 7.8mV 4.7mV ADM1060 INPUTS VH = Desired Hysteresis Voltage NTHRESH = Decimalized version of 5 bit hysteresis code Therefore, if the low range threshold detector was selected (ie) 1V to 3V (VR), the max hysteresis is then defined as:(3V-1V) x 31/255 = 242mV (25-1 =31) The hysteresis programming resolution is the same as the threshold detect ranges (ie) 37.5mV on the high range, 15.6mV on the mid range, 7.8mV on the low range and 4.7mV on the ultra low range. BIPOLAR SFD'S The 2 bipolar SFD's also allow the detection of faults on negative supplies. A polarity bit in the setup register for this SFD (bit 7- register BSnSEL- see register map overleaf) determines if a positive or negative input should be applied to VBn. Only 1 range (-6V to -2V) is available when the SFD's are in negative mode. Note that the bipolar SFD's cannot be used to power the ADM1060, even if the voltage on VBn is positive. SFD FAULT TYPES 3 types of faults can be asserted by the SFD- 1) An OV fault, 2) an UV fault and 3) an out-of-window fault (where the UV and OV faults are OR'ed together). The type of fault required is programmed using the Fault Type Select bits (bits 0,1- Register _SnSEL). If an application requires separate fault conditions to be detected on one supply (eg) assert PDO1 if an UV fault occurs on a 3.3V supply, assert PDO9 if an OV fault occurs on the same 3.3V supply, that supply will need to be applied to more than one input pin. FAULT OUTPUT VPn Table 1. Input threshold Ranges and Resolution. Figure 2 illustrates the function of the programmable SFD (for the case of a positive supply). VPn RANGE SELECT DAC (1- BIT) OV Comparator Glitch Filter VREF GLITCH FILTERING ON THE SFD'S The final stage of the SFD is a glitch filter. This block provides time domain filtering on spurious transitions of the SFD fault output. These could be caused by bounce on a supply at its initial turn- on. The comparators of the SFD can have hysteresis digitally programmed into them to ensure smooth transitions but further deglitching is provided by the glitch filter stage. A fault must be asserted for greater than the programmed Glitch Filter timeout before it is seen at the output of the glitch filter. The max. programmable timeout period is 100 s. Both edges of the input are filtered by the same amount of time, so if the input pulse is longer than the glitch filter timeout and is seen at the output, the length of the output pulse is the same as the input pulse. If the input pulse is shorter than the programmed timeout, then nothing appears at the output. Figure 2 shows the implementation of glitch filtering. DUAL 8-BIT DAC FOR SETTING UV AND OV THRESHOLDS UV Comparator Fault Type select Figure 2. Positive Programmable Supply Fault Detector SFD COMPARATOR HYSTERESIS The OV and UV comparators, shown in figure 1, are always looking at VPn via a potential divider. In order to avoid chattering (multiple transitions when the input is very close to the threshold level set), these comparators have digitally progammable hysteresis. The UV and OV hysteresis can be programmed in two registers which are similar but separate to the UV or OV threshold registers. Only the 5 LSB's of these registers can be set. The hysteresis is added after the supply voltage goes out of tolerance. Thus, the user can determine how much above the UV threshold the input must rise again before a UV fault is de-asserted. Similarly, the user can determine how much below the OV threshold the input must fall again before an OV fault is de-asserted. The hysteresis figure is given by:VH =VR x NTHRESH /255 where:- -8- REV. PrJ 11/02 PRELIMINARY TECHNICAL DATA ADM1060 INPUTS GLITCH FILTER INPUT PROGRAMMED TIMEOUT PROGRAMMED TIMEOUT ADM1060 PROGRAMMING THE SFD'S ON THE SMBUS The details of using the SMBus are described later, but the register names associated with the Supply Fault Detector blocks, the bitmap of those registers, and the function of each of the bits is described in the following tables. The tables show how to set up UV threshold, UV hysteresis, OV threshold, OV hysteresis, glitch filtering and fault type for each of the SFD's on the ADM1060. T0 TGF T0 TGF T0 TGF T0 TGF GLITCH FILTER OUTPUT Figure 3 . Glitch Filtering on the SFD's SFD REGISTER NAMES TABLE 2. LIST OF REGISTERS FOR THE SUPPLY FAULT DETECTORS Hex Address A0 A1 A2 A3 A4 A8 A9 AA AB AC B0 B1 B2 B3 B4 B8 B9 BA BB BC C0 C1 Table Name Default Power On Value FFh 00h 00h 00h 00h FFh 00h 00h 00h 00h FFh 00h 00h 00h 00h FFh 00h 00h 00h 00h FFh 00h Description 3 4 5 6 7 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 13 14 BS1OVTH BS1OVHYST BS1UVTH BS1UVHYST BS1SEL BS2OVTH BS2OVHYST BS2UVTH BS2UVHYST BS2SEL HSOVTH HSOVHYST HSUVTH HSUVHYST HSSEL PS1OVTH PS1OVHYST PS1UVTH PS1UVHYST PS1SEL PS2OVTH PS2OVHYST Overvoltage Threshold for Bipolar Voltage SFD1 (BS1SFD) Digital Hysteresis on OV threshold for BS1SFD Undervoltage Threshold for BS1SFD Digital Hysteresis on UV threshold for BS1SFD Glitch filter, Range and Fault Type select for BS1SFD Overvoltage Threshold for Bipolar Voltage SFD2 (BS2SFD) Digital Hysteresis on OV threshold for BS2SFD Undervoltage Threshold for BS2SFD Digital Hysteresis on UV threshold for BS2SFD Glitch filter, Range and Fault Type select for BS2SFD Overvoltage Threshold for High Voltage SFD Digital Hysteresis on OV threshold for HVSFD Undervoltage Threshold for HVSFD Digital Hysteresis on UV threshold for HVSFD Glitch filter, Range and Fault Type select for HVSFD Overvoltage Threshold for Positive Voltage SFD1 (PS1SFD) Digital Hysteresis on OV threshold for PS1SFD Undervoltage Threshold for PS1SFD Digital Hysteresis on UV threshold for PS1SFD Glitch filter, Range and Fault Type select for PS1SFD Overvoltage Threshold for Positive Voltage SFD2 (PS2SFD) Digital Hysteresis on OV threshold for PS2SFD (HVSFD) REV. PrJ 11/02 -9- PRELIMINARY TECHNICAL DATA ADM1060 Hex Address C2 C3 C4 C8 C9 CA CB CC D0 D1 D2 D3 D4 Table 15 16 17 13 14 15 16 17 13 14 15 16 17 Name PS2UVTH PS2UVHYST PS2SEL PS3OVTH PS3OVHYST PS3UVTH PS3UVHYST PS3SEL PS4OVTH PS4OVHYST PS4UVTH PS4UVHYST PS4SEL Default Power On Value 00h 00h 00h FFh 00h 00h 00h 00h FFh 00h 00h 00h 00h Description Undervoltage Threshold for PS2SFD Digital Hysteresis on UV threshold for PS2SFD Glitch filter, Range and Fault Type select for PS2SFD Overvoltage Threshold for Positive Voltage SFD3 (PS3SFD) Digital Hysteresis on OV threshold for PS3SFD Undervoltage Threshold for PS3SFD Digital Hysteresis on UV threshold for PS3SFD Glitch filter, Range and Fault Type select for PS3SFD Overvoltage Threshold for Positive Voltage SFD4 (PS4SFD) Digital Hysteresis on OV threshold for PS4SFD Undervoltage Threshold for PS4SFD Digital Hysteresis on UV threshold for PS4SFD Glitch filter, Range and Fault Type select for PS4SFD ADM1060 INPUTS TABLE 2. LIST OF REGISTERS FOR THE SUPPLY FAULT DETECTORS (Contd.) -10- REV. PrJ 11/02 PRELIMINARY TECHNICAL DATA ADM1060 INPUTS SFD REGISTER BITMAPS BIPOLAR SUPPLY FAIL DETECT (BSnSFD) REGISTERS TABLE 3. REGISTER A0H,A8H BSnOVTH (POWER- ON DEFAULT FFH) Bit 7-0 Name OV7-OV0 R/W R/W Description 8 bit digital value for overvoltage threshold on BSn SFD. ADM1060 TABLE 4. REGISTER A1H,A9H BSnOVHYST (POWER- ON DEFAULT 00H) Bit 7-5 4-0 Name Reserved HY4-HY0 R/W N/A R/W Description Cannot be used 5 bit digital value for hysteresis on OV threshold of BSn SFD TABLE 5. REGISTER A2H,AAH BSnUVTH (POWER- ON DEFAULT 00H) Bit 7-0 Name UV7-UV0 R/W R/W Description 8 bit digital value for undervoltage threshold on BSn SFD TABLE 6. REGISTER A3H,ABH BSnUVHYST (POWER- ON DEFAULT 00H) Bit 7-5 4-0 Name Reserved HY4-HY0 R/W N/A R/W Description Cannot be used 5 bit digital value for hysteresis on UV threshold of BSn SFD TABLE 7. REGISTER A4H,ACH BSnSEL (POWER- ON DEFAULT 00H) Bit 7 Name POL R/W R/W Description Polarity of Bipolar SFDn POL Sign of Detection Range 0 Positive 1 Negative GF2 0 0 0 0 1 1 1 1 GF1 0 0 1 1 0 0 1 1 GF0 0 1 0 1 0 1 0 1 Glitch Filter Delay ( s) 0 5 10 20 30 50 75 100 6-4 GF2-GF0 R/W 3 2 Reserved RSEL N/A R/W Cannot be used Note: When POL is set to 1 (ie) SFD is in negative mode, then RSEL is unused since there is only one range in this mode. RSEL1 Bottom of Top of Step Size (mV) Range Range 0 1V 3V 7.8 1 2V 6V 15.6 FS1 0 0 1 1 FS0 0 1 0 1 Fault Select Type Overvoltage Undervoltage Out-of-Window Not Allowed 1-0 FS1-FS0 R/W REV. PrJ 11/02 -11- PRELIMINARY TECHNICAL DATA ADM1060 TABLE 8. REGISTER B0H HSOVTH (POWER- ON DEFAULT FFH) Bit 7-0 Name OV7-OV0 R/W R/W Description 8 bit digital value for overvoltage threshold on HV SFD. ADM1060 INPUTS HIGHVOLTAGE SUPPLY FAULT DETECT (HVSFD) REGISTERS TABLE 9. REGISTER B1H HSOVHYST (POWER- ON DEFAULT 00H) Bit 7-5 4-0 Name Reserved HY4-HY0 R/W N/A R/W Description Cannot be used 5 bit digital value for hysteresis on OV threshold of HV SFD TABLE 10. REGISTER B2H HSUVTH (POWER- ON DEFAULT 00H) Bit 7-0 Name UV7-UV0 R/W R/W Description 8 bit digital value for undervoltage threshold on HV SFD TABLE 11. REGISTER B3H HSUVHYST (POWER- ON DEFAULT 00H) Bit 7-5 4-0 Name Reserved HY4-HY0 R/W N/A R/W Description Cannot be used 5 bit digital value for hysteresis on UV threshold of HV SFD TABLE 12. REGISTER B4H HSSEL (POWER- ON DEFAULT 00H) Bit 7 6-4 Name Reserved GF2-GF0 R/W N/A R/W Description Cannot be used GF2 0 0 0 0 1 1 1 1 RSEL 0 1 1-0 FS1-FS0 W FS1 0 0 1 1 GF1 0 0 1 1 0 0 1 1 GF0 0 1 0 1 0 1 0 1 Glitch Filter Delay ( s) 0 5 10 20 30 50 75 100 Top of Range 6V 14.4V Step Size (mV) 15.6 37.6 3 2 Reserved RSEL N/A W Cannot be used Bottom of Range 2V 4.8V FS0 0 1 0 1 Fault Select Type Overvoltage Undervoltage Out-of-Window Not Allowed -12- REV. PrJ 11/02 PRELIMINARY TECHNICAL DATA ADM1060 INPUTS TABLE 13. REGISTER B8H,C0H,C8H,D0H Bit 7-0 Name OV7-OV0 ADM1060 PSNOVTH (POWER- ON DEFAULT FFH) R/W R/W Description 8 bit digital value for overvoltage threshold on PSn SFD. POSITIVE VOLTAGE SUPPLY FAULT DETECT (PSNSFD) REGISTERS TABLE 14. REGISTER B9H,C1H,C9H,D1H PSnOVHYST (POWER- ON DEFAULT 00H) Bit 7-5 4-0 Name Reserved HY4-HY0 R/W N/A R/W Description Cannot be used 5 bit digital value for hysteresis on OV threshold of PSn SFD TABLE 15. REGISTER BAH,C2H,CAH,D2H Bit 7-0 Name UV7-UV0 PSnUVTH (POWER- ON DEFAULT 00H) W R/W Description 8 bit digital value for undervoltage threshold on PSn SFD TABLE 16. REGISTER BBH,C3H,CBH,D3H PSnUVHYST (POWER- ON DEFAULT 00H) Bit 7-5 4-0 Name Reserved HY4-HY0 W N/A R/W Description Cannot be used 5 bit digital value for hysteresis on UV threshold of PSn SFD TABLE 17. REGISTER BCH,C4H,CCH,D4H Bit 7 6-4 Name Reserved GF2-GF0 PSnSEL (POWER- ON DEFAULT 00H) R/W N/A R/W Description Cannot be used GF2 0 0 0 0 1 1 1 1 RSEL1 0 0 1 GF1 0 0 1 1 0 0 1 1 RSEL0 0 1 X FS0 0 1 0 1 GF0 0 1 0 1 0 1 0 1 Glitch Filter Delay ( s) 0 5 10 20 30 50 75 100 Top of Range 6V 3V 1.8V Step Size (mV) 15.6 7.8 4.7 3-2 RSEL1-RESL0 R/W Bottom of Range 2V 1V 0.6V Fault Select Type Overvoltage Undervoltage Out-of-Window Not Allowed 1-0 FS1-FS0 R/W FS1 0 0 1 1 REV. PrJ 11/02 -13- PRELIMINARY TECHNICAL DATA ADM1060 WATCHDOG FAULT DETECTOR ADM1060 INPUTS can also be inverted, if required (eg) if a high- low- high pulse was required by a processor to reset. Thus, a fault on the watchdog can be used to generate a pulsed or latched output on any or all of the 9 PDO's. The latched signal can be cleared low by reading LATF1, then LATF2 across the SMBus interface (see Fault Registers section). The RAM register list and the bit map for the Watchdog Fault Detector are shown below. The ADM1060 has a Watchdog Fault Detector. This can be used to monitor a processor clock to ensure normal operation. The detector monitors the WDI pin, expecting there to be a low-to-high or high to low transition within a preprogrammed period. The watchdog timeout period can be programmed from 200msec to a maximum of 12.8sec. If no transition is detected, 2 signals are asserted. One is a latched high signal, indicating a fault has occurred. The other signal is a low- high- low pulse which can be used as a RESET signal for a processor core. The width of this pulse can be programmed (from 10 s to a maximum of 10ms). These two Watchdog signals can be selected as inputs to each of the PLB's (see PLBA section). They TABLE 18. LIST OF REGISTERS FOR WATCHDOG FAULT DETECTOR Hex Address 9C Table Name Default Power On Value 00h Description 19 WDCFG Program length Watchdog timeout and length of pulsed output TABLE 19. REGISTER 9CH WDCFG (POWER- ON DEFAULT 00H) Bit Name R/W Description 7-5 4-3 Reserved PULS1-PULS0 R/W R/W Unused Length of pulse outputted once the Watchdog Detector has timed out PULS1 PULS0 Pulse Length Selected ( s) 0 0 1 1 2-0 PER3-PER0 R/W 0 1 0 1 10 100 1000 10000 Watchdog Timeout Period PER2 PER1 PER0 Watchdog Timeout selected (ms) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Disabled 200 400 800 1600 3200 6400 12800 -14- REV. PrJ 11/02 PRELIMINARY TECHNICAL DATA ADM1060 INPUTS GENERAL PURPOSE INPUTS (GPI'S) ADM1060 filter can be used to debounce a Manual Reset switch. The length of the glitch filter can also be programmed. LOGIC STATE OF THE GPI'S (AND OTHER LOGIC INPUTS) The ADM1060 has 4 General Purpose Logic Inputs (GPI's). These are TTL/CMOS logic level compatible. Standard logic signals can be applied to the pins (eg) RESET from reset generators, PWRGOOD signals, Fault flags, Manual Resets etc. These signals can be gated with the other inputs supervised by the ADM1060, and used to control the status of the PDO's. The inputs can be simply buffered, or a logic transition can be detected and a pulse output generated. The width of this pulse is programmable from 10 s to a maximum of 10ms. The configuration of the GPI's is shown in the register and bitmaps below. The GPI's also feature a glitch filter, similar to that provided on the SFD's. This enables the user to ignore spurious transitions on the GPI's. For example, the glitch Each of the GPI's has a weak (10 A) pull-down current source. The current sources can be connected to the inputs by progamming the relevant bit in a register (PDEN). This enables the user to control the condition of these inputs, pulling them to GND, even when they are unused or left floating. Note that the same pull- down function is provided for the SMBus address pins, A0 and A1 and for the WDI pin. A register is used to program which of the inputs is connected to the current sources. TABLE 20. LIST OF REGISTERS FOR THE GENERAL PURPOSE INPUTS (GPIN) Hex Address 98 Table Name Default Power On Value 00h Description GPI4CFG Setup of the glitch filter delay, pulse width, level/edge detection etc. configuration of GPI4 Setup of the glitch filter delay, pulse width, level/edge detection etc. configuration of GPI3 Setup of the glitch filter delay, pulse width, level/edge detection etc. configuration of GPI2 Setup of the glitch filter delay, pulse width, level/edge detection etc. configuration of GPI1 99 GPI3CFG 00h 9A GPI2CFG 00h 9B GPI1CFG 00h TABLE 21. BIT MAP FOR GPInCFG REGISTERS (POWER- ON DEFAULT 00H) Bit Name R/W Description 7 6 5 Reserved INVIN INTYP N/A R/W R/W Cannot be used If high, invert Input Determines whether a level or an edge is detected on the pin. If an edge is detected then positive pulse of programmable length is outputted INTYP Detect 0 1 4-3 PULS1-0 R/W Detect level Detect edge Length of pulse outputted once an edge has been detected on input PULS1 PULS0 Pulse Length Selected ( s) 0 0 1 1 2-0 GF2-GF0 R/W 0 1 0 1 10 100 1000 10000 Length of time for which the input is ignored GF2 GF1 GF0 Glitch Filter Delay ( s) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 5 10 20 30 50 75 100 REV. PrJ 11/02 -15- PRELIMINARY TECHNICAL DATA ADM1060 Hex Address 91 Table Name Default Power On Value 00h Description ADM1060 INPUTS TABLE 22. LIST OF REGISTERS FOR THE PULL- DOWN CURRENT SOURCES ON LOGIC INPUTS PDEN Setup of the Pull- down current sources on all logic inputs. Pulls the selected input to GND TABLE 23. BIT MAP FOR PDEN REGISTER- 91H (POWER- ON DEFAULT 00H) Bit Name R/W Description 7 6 5 4 3 2 1 0 Reserved PDENA1 PDENA0 PDENWDI PDENGPI4 PDENGPI3 PDENGPI2 PDENGPI1 N/A R/W R/W R/W R/W R/W R/W R/W Cannot be used If high, then address pin A1 is pulled to GND using a 10uA pull- down current source. If high, then address pin A0 is pulled to GND using a 10uA pull- down current source. If high, then WDI is pulled to GND using a 10 A pull- down current source. If high, then GPI4 is pulled to GND using a 10 A pull- down current source. If high, then GPI3 is pulled to GND using a 10 A pull- down current source. If high, then GPI2 is pulled to GND using a 10 A pull- down current source. If high, then GPI1 is pulled to GND using a 10 A pull- down current source. -16- REV. PrJ 11/02 PRELIMINARY TECHNICAL DATA PROGRAMMING ADM1060 PROGRAMMABLE LOGIC BLOCK ARRAY ADM1060 inverting gate shown is an X-OR gate, resulting in the following truth table:POL 0 0 1 1 INPUT SIGNAL 0 1 0 1 X-OR OUTPUT 0 1 1 0 The ADM1060 contains a Programmable Logic Block Array (PLBA). This block is the logical core of the device. The PLBA (and the PDBs- see next section) is what provides the sequencing function of the ADM1060. The assertion of the 9 Programmable Driver Outputs (PDO) is controlled by the PLBA. The PLBA comprises of 9 macrocells, 1 per PDO Channel. The main components of the macrocells are 2 Wide AND- OR gates, as shown in Figure 4. Each AND gate represents a function (A and B) which can be used independently to control the assertion of the PDO pin. There are 21 inputs to each of these AND gates. These are:- Table 25. Truth Table for PLB Input Inversion The last 2 entries in the truth table show, that with the INVERT bit set, the X-OR output is always the inverse of the input. Similarly, the ignore gate shown is an OR gate, resulting in the following truth table:IMK 0 0 1 1 INPUT SIGNAL 0 1 0 1 OR OUTPUT 0 1 1 1 * The logic outputs of all 7 of the Supply Fault Detectors * The 4 GPI logic inputs * The Watchdog fault detector (Latched and Pulsed) * The delayed output of any of the other macrocells (the output of a macrocell cannot be an input to itself, since this would result in a non- terminating loop). All 21 inputs are hardwired to both function A and function B AND gates. The user can then select which of these inputs controls the output. This is done using 2 control signals, IMK (a masking bit, setting it ignores the relevant input) and POL (a polarity bit, setting it inverts the input before it is applied to the AND gate). The effect of setting these bits can be seen in figure 4 below. The SIGNAL INPUTS Table 26 Truth Table for PLB Input Masking It can be seen here that once the IMK bit is set the OR output is always 1, regardless of the input, thus ignoring it. Overleaf is a detailed diagram of the 21 inputs and the registers required to program them. Those shown are just for function A of PLB1 but function B and all of the functions in the other 8 PLB's are programmed exactly the same way. An Enable register allows the user to use function A or B or both. The output of functions A and/ or B is inputted to a Programmable Delay Block (PDB) where a delay can be programmed on both the rising and falling edge of an input (see next section). The output of this PDB block can be progammed to invert before one or any of the PDO pins is asserted. The control bits for these macrocells are stored locally in latches which are loaded at power up. These latches can also be updated via the serial interface. The registers containing the macrocell control bits, and the function of each bit are defined in the tables overleaf. POL (INVERT) ENABLE FUNCTION A IMK ( IGNORE) 2 wide AND gates (20 inputs) PROGRAMMABLE DELAY BLOCK PLBOUT INVERT OUTPUT ENABLE FUNCTION B Figure 4. Simplified Programmable Logic Block Macrocell Schematic REV. PrJ 11/02 -17- PRELIMINARY TECHNICAL DATA ADM1060 (ie) Not Connected ADM1060 LOGIC The diagram shown highlights all 21 inputs to a given function and the register/ bits which need to be set in order to condition the 21 inputs correctly. The diagram only shows function A of Programmable Logic Block 1 (PLB1) but all functions are programmed in the same way. If, as an example, the user wishes to assert PLBOUT 200ms after all of the supplies are in spec. (PLBOUT may be used to drive the enable pin of an LDO) then the supply fault detectors VBn, VH and VPn are required to control the function. The function is programmed as follows:* The IGNORE bit of all the other inputs (GPI's, PDB's WDI) in the relevant P1xxxIMK registers is set to 1. Thus, regardless of their status, the input to the function AND gate for these inputs will be 1. * Since the SFD's assert a 1 under a fault condition and a 0 when the supplies are in tolerance, the SFD outputs need to be inverted before being applied to the function. Thus the relevant bit in the P1SFDPOL register is set (See Table Y). * The function is enabled (bit 1 of register P1EN- Table Z)) * A rise time of 200ms is programmed (register P1PDBTIM- see register map overleaf for details) ENABLE FUNCTION A 07H P1EN.1 RISE TIME 0CH P1PDBTIM.7-4 PLB1 PLB2 INVERT 00H P1PLBPOLA.0 IGNORE 01H P1PLBIMKA.0 PLB3 INVERT 00H P1PLBPOLA.1 IGNORE 01H P1PLBIMKA.1 PLB4 INVERT 00H P1PLBPOLA.2 IGNORE 01H P1PLBIMKA.2 PLB5 INVERT 00H P1PLBPOLA.3 IGNORE 01H P1PLBIMKA.3 PLB6 INVERT 00H P1PLBPOLA.4 IGNORE 01H P1PLBIMKA.4 PLB7 INVERT 00H P1PLBPOLA.5 IGNORE 01H P1PLBIMKA.5 PLB8 INVERT 00H P1PLBPOLA.6 IGNORE 01H P1PLBIMKA.6 PLB9 INVERT 00H P1PLBPOLA.7 IGNORE 01H P1PLBIMKA.7 VB1 INVERT 02H P1SFDPOLA.0 IGNORE 03H P1SFDIMKA.0 VB2 INVERT 02H P1SFDPOLA.1 IGNORE 03H P1SFDIMKA.1 VH INVERT 02H P1SFDPOLA.2 IGNORE 03H P1SFDIMKA.2 VP1 INVERT 02H P1SFDPOLA.3 IGNORE 03H P1SFDIMKA.3 PDB PLBOUT VP2 INVERT 02H P1SFDPOLA.4 IGNORE 03H P1SFDIMKA.4 TO FUNCTION B 0CH P1PDBTIM.3-0 FALL TIME 07H P1EN.2 VP3 INVERT 02H P1SFDPOLA.5 IGNORE 03H P1SFDIMKA.5 VP4 INVERT 02H P1SFDPOLA.6 IGNORE 03H P1SFDIMKA.6 GPI1 INVERT 04H P1GPIPOL.4 IGNORE 05H P1GPIIMK.4 GPI2 INVERT 04H P1GPIPOL.5 IGNORE 05H P1GPIIMK.5 GPI3 INVERT 04H P1GPIPOL.6 IGNORE 05H P1GPIIMK.6 GPI4 INVERT 04H P1GPIPOL.7 IGNORE 05H P1GPIIMK.7 WDI_P INVERT 06H P1WDICFG.7 IGNORE 06H P1WDICFG.6 WDI_L INVERT 06H P1WDICFG.5 IGNORE 06H P1WDICFG.4 Figure 5. Detailed Diagram for function A of PLB1 -18- REV. PrJ 11/02 PRELIMINARY TECHNICAL DATA ADM1060 LOGIC PLBA REGISTER NAMES TABLE 27. LIST OF REGISTERS FOR THE PROGRAMMABLE LOGIC BLOCK ARRAY (PLBA) Hex Address 00 Table Name Default Power On Value 00h Description ADM1060 28 P1PLBPOLA Polarity Sense for all 8 other PLB outputs when used as inputs to the A function of PLB1 Ignore Mask for all 8 other PLB outputs when used as inputs to the A function of PLB1 Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the A function of PLB1 Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the A function of PLB1 Polarity Sense and Ignore Mask bits for all 4 GPI's when used as inputs to the A function of PLB1 Polarity Sense and Ignore Mask bits for all 4 GPI's when used as inputs to the B function of PLB1 Polarity Sense and Ignore Mask bits for the pulsed and latched outputs of the watchdog detector when used as inputs to both A and B functions of PLB1 Enable bits for A and B functions of PLB1, polarity bit for PLB1 output Polarity Sense for all 8 other PLB outputs when used as inputs to the B function of PLB1 Ignore Mask for all 8 other PLB outputs when used as inputs to the B function of PLB1 Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the B function of PLB1 Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the B function of PLB1 Polarity Sense for all 8 other PLB outputs when used as inputs to the A function of PLB2 Ignore Mask for all 8 other PLB outputs when used as inputs to the A function of PLB2 Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the A function of PLB2 Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the A function of PLB2 Polarity Sense and Ignore Mask bits for all 4 GPI's when used as inputs to the A function of PLB2 Polarity Sense and Ignore Mask bits for all 4 GPI's when used as inputs to the B function of PLB2 Polarity Sense and Ignore Mask bits for the pulsed and latched outputs of the watchdog detector when used as inputs to both A and B functions of PLB2 Enable bits for A and B functions of PLB2, polarity bit for PLB2 output Polarity Sense for all 8 other PLB outputs when used as inputs to the B function of PLB2 01 29 P1PLBIMKA 00h 02 30 P1SFDPOLA 00h 03 31 P1SFDIMKA 00h 04 32 P1GPIPOL 00h 05 33 P1GPIIMK 00h 06 34 P1WDICFG 00h 07 35 PS1EN 00h 08 28 P1PLBPOLB 00h 09 29 P1PLBIMKB 00h 0A 30 P1SFDPOLB 00h 0B 31 P1SFDIMKB 00h 10 28 P2PLBPOLA 00h 11 29 P2PLBIMKA 00h 12 30 P2SFDPOLA 00h 13 31 P2SFDIMKA 00h 14 32 P2GPIPOL 00h 15 33 P2GPIIMK 00h 16 34 P2WDICFG 00h 17 35 PS2EN 00h 18 28 P2PLBPOLB 00h REV. PrJ 11/02 -19- PRELIMINARY TECHNICAL DATA ADM1060 Hex Address 19 Table 29 Name P2PLBIMKB Default Power On Value 00h Description Ignore Mask for all 8 other PLB outputs when used as inputs to the B function of PLB2 Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the B function of PLB2 Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the B function of PLB2 Polarity Sense for all 8 other PLB outputs when used as inputs to the A function of PLB3 Ignore Mask for all 8 other PLB outputs when used as inputs to the A function of PLB3 Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the A function of PLB3 Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the A function of PLB3 Polarity Sense and Ignore Mask bits for all 4 GPI's when used as inputs to the A function of PLB3 Polarity Sense and Ignore Mask bits for all 4 GPI's when used as inputs to the B function of PLB3 Polarity Sense and Ignore Mask bits for the pulsed and latched outputs of the watchdog detector when used as inputs to both A and B functions of PLB3 Enable bits for A and B functions of PLB3, polarity bit for PLB3 output Polarity Sense for all 8 other PLB outputs when used as inputs to the B function of PLB3 Ignore Mask for all 8 other PLB outputs when used as inputs to the B function of PLB3 Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the B function of PLB3 Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the B function of PLB3 Polarity Sense for all 8 other PLB outputs when used as inputs to the A function of PLB1 Ignore Mask for all 8 other PLB outputs when used as inputs to the A function of PLB1 Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the A function of PLB1 Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the A function of PLB1 Polarity Sense and Ignore Mask bits for all 4 GPI's when used as inputs to the A function of PLB1 Polarity Sense and Ignore Mask bits for all 4 GPI's when used as inputs to the B function of PLB1 Polarity Sense and Ignore Mask bits for the pulsed and latched outputs of the watchdog detector when used as inputs to both A and B functions of PLB4 Enable bits for A and B functions of PLB4, polarity bit for PLB4 output ADM1060 LOGIC TABLE 27. LIST OF REGISTERS FOR THE PROGRAMMABLE LOGIC BLOCK ARRAY (PLBA) (Contd.) 1A 30 P2SFDPOLB 00h 1B 31 P2SFDIMKB 00h 20 28 P3PLBPOLA 00h 21 29 P3PLBIMKA 00h 22 30 P3SFDPOLA 00h 23 31 P3SFDIMKA 00h 24 32 P3GPIPOL 00h 25 33 P3GPIIMK 00h 26 34 P3WDICFG 00h 27 35 PS3EN 00h 28 28 P3PLBPOLB 00h 29 29 P3PLBIMKB 00h 2A 30 P3SFDPOLB 00h 2B 31 P3SFDIMKB 00h 30 28 P4PLBPOLA 00h 31 29 P4PLBIMKA 00h 32 30 P4SFDPOLA 00h 33 31 P4SFDIMKA 00h 34 32 P4GPIPOL 00h 35 33 P4GPIIMK 00h 36 34 P4WDICFG 00h 37 35 PS4EN 00h -20- REV. PrJ 11/02 PRELIMINARY TECHNICAL DATA ADM1060 LOGIC Hex Address 38 Table 28 Name P4PLBPOLB Default Power On Value 00h Description Polarity Sense for all 8 other PLB outputs when used as inputs to the B function of PLB4 Ignore Mask for all 8 other PLB outputs when used as inputs to the B function of PLB4 Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the B function of PLB4 Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the B function of PLB4 Polarity Sense for all 8 other PLB outputs when used as inputs to the A function of PLB5 Ignore Mask for all 8 other PLB outputs when used as inputs to the A function of PLB5 Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the A function of PLB5 Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the A function of PLB5 Polarity Sense and Ignore Mask bits for all 4 GPI's when used as inputs to the A function of PLB5 Polarity Sense and Ignore Mask bits for all 4 GPI's when used as inputs to the B function of PLB5 Polarity Sense and Ignore Mask bits for the pulsed and latched outputs of the watchdog detector when used as inputs to both A and B functions of PLB5 Enable bits for A and B functions of PLB5, polarity bit for PLB5 output Polarity Sense for all 8 other PLB outputs when used as inputs to the B function of PLB5 Ignore Mask for all 8 other PLB outputs when used as inputs to the B function of PLB5 Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the B function of PLB5 Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the B function of PLB5 Polarity Sense for all 8 other PLB outputs when used as inputs to the A function of PLB6 Ignore Mask for all 8 other PLB outputs when used as inputs to the A function of PLB6 Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the A function of PLB6 Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the A function of PLB6 Polarity Sense and Ignore Mask bits for all 4 GPI's when used as inputs to the A function of PLB6 Polarity Sense and Ignore Mask bits for all 4 GPI's used as inputs to the B function of PLB6 Description ADM1060 TABLE 27. LIST OF REGISTERS FOR THE PROGRAMMABLE LOGIC BLOCK ARRAY (PLBA) (Contd.) 39 29 P4PLBIMKB 00h 3A 30 P4SFDPOLB 00h 3B 31 P4SFDIMKB 00h 40 28 P5PLBPOLA 00h 41 29 P5PLBIMKA 00h 42 30 P5SFDPOLA 00h 43 31 P5SFDIMKA 00h 44 32 P5GPIPOL 00h 45 33 P5GPIIMK 00h 46 34 P5WDICFG 00h 47 35 PS5EN 00h 48 28 P5PLBPOLB 00h 49 29 P5PLBIMKB 00h 4A 30 P5SFDPOLB 00h 4B 31 P5SFDIMKB 00h 50 28 P6PLBPOLA 00h 51 29 P6PLBIMKA 00h 52 30 P6SFDPOLA 00h 53 31 P6SFDIMKA 00h 54 32 P6GPIPOL 00h 55 when Hex Address 33 P6GPIIMK 00h Table Name Default Power On Value REV. PrJ 11/02 -21- PRELIMINARY TECHNICAL DATA ADM1060 Hex Address 56 Table 34 Name P6WDICFG Default Power On Value 00h Description Polarity Sense and Ignore Mask bits for the pulsed and latched outputs of the watchdog detector when used as inputs to both A and B functions of PLB6 Enable bits for A and B functions of PLB6, polarity bit for PLB6 output Polarity Sense for all 8 other PLB outputs when used as inputs to the B function of PLB6 Ignore Mask for all 8 other PLB outputs when used as inputs to the B function of PLB6 Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the B function of PLB6 Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the B function of PLB6 Polarity Sense for all 8 other PLB outputs when used as inputs to the A function of PLB7 Ignore Mask for all 8 other PLB outputs when used as inputs to the A function of PLB7 Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the A function of PLB7 Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the A function of PLB7 Polarity Sense and Ignore Mask bits for all 4 GPI's when used as inputs to the A function of PLB7 Polarity Sense and Ignore Mask bits for all 4 GPI's when used as inputs to the B function of PLB7 Polarity Sense and Ignore Mask bits for the pulsed and latched outputs of the watchdog detector when used as inputs to both A and B functions of PLB7 Enable bits for A and B functions of PLB7, polarity bit for PLB7 output Polarity Sense for all 8 other PLB outputs when used as inputs to the B function of PLB7 Ignore Mask for all 8 other PLB outputs when used as inputs to the B function of PLB7 Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the B function of PLB7 Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the B function of PLB7 Polarity Sense for all 8 other PLB outputs when used as inputs to the A function of PLB8 Ignore Mask for all 8 other PLB outputs when used as inputs to the A function of PLB8 Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the A function of PLB8 Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the A function of PLB8 Polarity Sense and Ignore Mask bits for all 4 GPI's when used as inputs to the A function of PLB8 ADM1060 LOGIC TABLE 27. LIST OF REGISTERS FOR THE PROGRAMMABLE LOGIC BLOCK ARRAY (PLBA) (Contd.) 57 35 PS6EN 00h 58 28 P6PLBPOLB 00h 59 29 P6PLBIMKB 00h 5A 30 P6SFDPOLB 00h 5B 31 P6SFDIMKB 00h 60 28 P7PLBPOLA 00h 61 29 P7PLBIMKA 00h 62 30 P7SFDPOLA 00h 63 31 P7SFDIMKA 00h 64 32 P7GPIPOL 00h 65 33 P7GPIIMK 00h 66 34 P7WDICFG 00h 67 35 PS7EN 00h 68 28 P7PLBPOLB 00h 69 29 P7PLBIMKB 00h 6A 30 P7SFDPOLB 00h 6B 31 P7SFDIMKB 00h 70 28 P8PLBPOLA 00h 71 29 P8PLBIMKA 00h 72 30 P8SFDPOLA 00h 73 31 P8SFDIMKA 00h 74 32 P8GPIPOL 00h -22- REV. PrJ 11/02 PRELIMINARY TECHNICAL DATA ADM1060 LOGIC Hex Address 75 Table 33 Name P8GPIIMK Default Power On Value 00h Description Polarity Sense and Ignore Mask bits for all 4 GPI's when used as inputs to the B function of PLB8 Polarity Sense and Ignore Mask bits for the pulsed and latched outputs of the watchdog detector when used as inputs to both A and B functions of PLB8 Enable bits for A and B functions of PLB8, polarity bit for PLB8 output Polarity Sense for all 8 other PLB outputs when used as inputs to the B function of PLB8 Ignore Mask for all 8 other PLB outputs when used as inputs to the B function of PLB8 Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the B function of PLB8 Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the B function of PLB8 Polarity Sense for all 8 other PLB outputs when used as inputs to the A function of PLB9 Ignore Mask for all 8 other PLB outputs when used as inputs to the A function of PLB9 Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the A function of PLB9 Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the A function of PLB9 Polarity Sense and Ignore Mask bits for all 4 GPI's when used as inputs to the A function of PLB9 Polarity Sense and Ignore Mask bits for all 4 GPI's when used as inputs to the B function of PLB9 Polarity Sense and Ignore Mask bits for the pulsed and latched outputs of the watchdog detector when used as inputs to both A and B functions of PLB9 Enable bits for A and B functions of PLB9, polarity bit for PLB9 output Polarity Sense for all 8 other PLB outputs when used as inputs to the B function of PLB9 Ignore Mask for all 8 other PLB outputs when used as inputs to the B function of PLB9 Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the B function of PLB9 Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP's) to the B function of PLB9 ADM1060 TABLE 27. LIST OF REGISTERS FOR THE PROGRAMMABLE LOGIC BLOCK ARRAY (PLBA) (Contd.) 76 34 P8WDICFG 00h 77 35 PS8EN 00h 78 28 P8PLBPOLB 00h 79 29 P8PLBIMKB 00h 7A 30 P8SFDPOLB 00h 7B 31 P8SFDIMKB 00h 80 28 P9PLBPOLA 00h 81 29 P9PLBIMKA 00h 82 30 P9SFDPOLA 00h 83 31 P9SFDIMKA 00h 84 32 P9GPIPOL 00h 85 33 P9GPIIMK 00h 86 34 P9WDICFG 00h 87 35 PS9EN 00h 88 28 P9PLBPOLB 00h 89 29 P9PLBIMKB 00h 8A 30 P9SFDPOLB 00h 8B 31 P9SFDIMKB 00h REV. PrJ 11/02 -23- PRELIMINARY TECHNICAL DATA ADM1060 PLBA REGISTER BITMAPS TABLE 28. BIT MAP FOR Bit ADM1060 LOGIC PnPLBPOLA/PnPLBPOLB REGISTERS (POWER- ON DEFAULT 00H) R/W Description Name 7-0 POL9-POL1 R/W PLB1 If high, invert the PLBn input before it is used in function A or B PLB2 10H 18H PLB9 PLB8 PLB7 PLB6 PLB5 PLB4 PLB3 PLB1 PLB3 20H 28H PLB9 PLB8 PLB7 PLB6 PLB5 PLB4 PLB2 PLB1 PLB4 30H 38H PLB9 PLB8 PLB7 PLB6 PLB5 PLB3 PLB2 PLB1 PLB5 40H 48H PLB9 PLB8 PLB7 PLB6 PLB4 PLB3 PLB2 PLB1 PLB6 50H 58H PLB9 PLB8 PLB7 PLB5 PLB4 PLB3 PLB2 PLB1 PLB7 60H 68H PLB9 PLB8 PLB6 PLB5 PLB4 PLB3 PLB2 PLB1 PLB8 70H 78H PLB9 PLB7 PLB6 PLB5 PLB4 PLB3 PLB2 PLB1 PLB9 80H 88H PLB8 PLB7 PLB6 PLB5 PLB4 PLB3 PLB2 PLB1 Function A Function B 7 6 5 4 3 2 1 0 00H 08H PLB9 PLB8 PLB7 PLB6 PLB5 PLB4 PLB3 PLB2 TABLE 29. BIT MAP FOR Bit 7-0 PnPLBIMKA/PnPLBIMKB REGISTERS (POWER- ON DEFAULT 00H) R/W Description R/W PLB1 If high, mask the PLBn input before it is used in function A or B PLB2 11H 19H PLB9 PLB8 PLB7 PLB6 PLB5 PLB4 PLB3 PLB1 PLB3 21H 29H PLB9 PLB8 PLB7 PLB6 PLB5 PLB4 PLB2 PLB1 PLB4 31H 39H PLB9 PLB8 PLB7 PLB6 PLB5 PLB3 PLB2 PLB1 PLB5 41H 49H PLB9 PLB8 PLB7 PLB6 PLB4 PLB3 PLB2 PLB1 PLB6 51H 59H PLB9 PLB8 PLB7 PLB5 PLB4 PLB3 PLB2 PLB1 PLB7 61H 69H PLB9 PLB8 PLB6 PLB5 PLB4 PLB3 PLB2 PLB1 PLB8 71H 79H PLB9 PLB7 PLB6 PLB5 PLB4 PLB3 PLB2 PLB1 PLB9 81H 89H PLB8 PLB7 PLB6 PLB5 PLB4 PLB3 PLB2 PLB1 Name IGN9-IGN1 Function A Function B 7 6 5 4 3 2 1 0 01H 09H PLB9 PLB8 PLB7 PLB6 PLB5 PLB4 PLB3 PLB2 TABLE 30. BIT MAP FOR Bit 7 6-0 Name PnSFDPOLA/PnSFDPOLB REGISTERS (POWER- ON DEFAULT 00H) R/W Description Cannot be used R/W PLB1 If high, invert the SFDn input before it is used in function A or B PLB2 12H 1AH VP4 VP3 VP2 VP1 PLB3 22H 2AH VP4 VP3 VP2 VP1 PLB4 32H 3AH VP4 VP3 VP2 VP1 PLB5 42H 4AH VP4 VP3 VP2 VP1 PLB6 52H 5AH VP4 VP3 VP2 VP1 PLB7 62H 6AH VP4 VP3 VP2 VP1 PLB8 72H 7AH VP4 VP3 VP2 VP1 PLB9 82H 8AH VP4 VP3 VP2 VP1 Reserved N/A POL7-POL1 Function A Function B 6 5 4 3 02H 0AH VP4 VP3 VP2 VP1 -24- REV. PrJ 11/02 PRELIMINARY TECHNICAL DATA ADM1060 LOGIC 2 1 0 VH VB2 VB1 VH VB2 VB1 VH VB2 VB1 VH VB2 VB1 VH VB2 VB1 VH VB2 VB1 VH VB2 VB1 ADM1060 VH VB2 VB1 VH VB2 VB1 TABLE 31. BIT MAP FOR Bit 7 6-0 PnSFDIMKA/PnSFDIMKB REGISTERS (POWER- ON DEFAULT 00H) R/W Description Cannot be used R/W PLB1 If high, mask the SFDn input before it is used in function A or B PLB2 13H 1BH VP4 VP3 VP2 VP1 VH VB2 VB1 PLB3 23H 2BH VP4 VP3 VP2 VP1 VH VB2 VB1 PLB4 33H 3BH VP4 VP3 VP2 VP1 VH VB2 VB1 PLB5 43H 4BH VP4 VP3 VP2 VP1 VH VB2 VB1 PLB6 53H 5BH VP4 VP3 VP2 VP1 VH VB2 VB1 PLB7 63H 6BH VP4 VP3 VP2 VP1 VH VB2 VB1 PLB8 73H 7BH VP4 VP3 VP2 VP1 VH VB2 VB1 PLB9 83H 8BH VP4 VP3 VP2 VP1 VH VB2 VB1 Name Reserved N/A IGN7-IGN1 Function A Function B 6 5 4 3 2 1 0 03H 0BH VP4 VP3 VP2 VP1 VH VB2 VB1 TABLE 32. BIT MAP FOR PnGPIPOL REGISTERS (POWER- ON DEFAULT 00H) Bit 7-4 3-0 Name R/W Description R/W R/W PLB1 04H 7 6 5 4 3 2 1 0 Function B Function A GPI1 GPI2 GPI3 GPI4 GPI1 GPI2 GPI3 GPI4 If high, invert the GPIn input before it is used in function A If high, invert the GPIn input before it is used in function B PLB2 PLB3 PLB4 PLB5 PLB6 PLB7 PLB8 14H GPI1 GPI2 GPI3 GPI4 GPI1 GPI2 GPI3 GPI4 24H GPI1 GPI2 GPI3 GPI4 GPI1 GPI2 GPI3 GPI4 34H GPI1 GPI2 GPI3 GPI4 GPI1 GPI2 GPI3 GPI4 44H GPI1 GPI2 GPI3 GPI4 GPI1 GPI2 GPI3 GPI4 54H GPI1 GPI2 GPI3 GPI4 GPI1 GPI2 GPI3 GPI4 64H GPI1 GPI2 GPI3 GPI4 GPI1 GPI2 GPI3 GPI4 74H GPI1 GPI2 GPI3 GPI4 GPI1 GPI2 GPI3 GPI4 PLB9 84H GPI1 GPI2 GPI3 GPI4 GPI1 GPI2 GPI3 GPI4 APOL4-APOL1 BPOL4-BPOL1 REV. PrJ 11/02 -25- PRELIMINARY TECHNICAL DATA ADM1060 TABLE 33. BIT MAP FOR PNGPIIMK REGISTERS (POWER- ON DEFAULT 00H) Bit 7-4 3-0 Name AIMK4-AIMK1 BIMK4-BIMK1 R/W R/W R/W Description If high, mask the GPIn input before it is used in function A If high, mask the GPIn input before it is used in function B PLB1 05H 7 6 5 4 3 2 1 0 Function B Function A GPI1 GPI2 GPI3 GPI4 GPI1 GPI2 GPI3 GPI4 PLB2 15H GPI1 GPI2 GPI3 GPI4 GPI1 GPI2 GPI3 GPI4 PLB3 25H GPI1 GPI2 GPI3 GPI4 GPI1 GPI2 GPI3 GPI4 PLB4 35H GPI1 GPI2 GPI3 GPI4 GPI1 GPI2 GPI3 GPI4 PLB5 45H GPI1 GPI2 GPI3 GPI4 GPI1 GPI2 GPI3 GPI4 PLB6 55H GPI1 GPI2 GPI3 GPI4 GPI1 GPI2 GPI3 GPI4 PLB7 65H GPI1 GPI2 GPI3 GPI4 GPI1 GPI2 GPI3 GPI4 PLB8 75H GPI1 GPI2 GPI3 GPI4 GPI1 GPI2 GPI3 GPI4 PLB9 85H GPI1 GPI2 GPI3 GPI4 GPI1 GPI2 GPI3 GPI4 ADM1060 LOGIC TABLE 34. PnWDICFG REGISTERS 06H,16H,26H,36H,46H,56H,66H,76H,86H (POWER- ON DEFAULT 00H) Bit 7 6 5 4 3 2 1 0 Name R/W APOLP R/W AIMKP R/W APOLL R / W AIMKL R/W BPOLP R/W BIMKP R/W BPOLL R/W BIMKL R/W Description If high, invert the pulsed WDI input before it is used in function A If high, mask the pulsed WDI input before it is used in function A If high, invert the latched WDI input before it is used in function A If high, mask the latched WDI input before it is used in function A If high, invert the pulsed WDI input before it is used in function B If high, mask the pulsed WDI input before it is used in function B If high, invert the latched WDI input before it is used in function B If high, mask the latched WDI input before it is used in function B TABLE 35. PnEN REGISTERS 07H,17H,27H,37H,47H,57H,67H,77H,87H (POWER- ON DEFAULT 00H) Bit 7-3 2 1 0 Name R/W Description Cannot be used If high, invert the PLB output If high, enable function A If high, enable function B Reserved N/A INVOP R/W ENA ENB R/W R/W -26- REV. PrJ 11/02 PRELIMINARY TECHNICAL DATA ADM1060 LOGIC PROGRAMMABLE DELAY BLOCK Each output of the PLBA is fed into a separate Programmable Delay Block (PDB). The PDB enables the user to add a delay to the logic block output before it is applied to either a PDO or one of the other PLB's (the output of a PLB can be the input to any of the other PLB's- not itself). The PDB operation is similar to that of the glitch filter (discussed in the SFD section). There is an important difference between the 2 functions, however. The delay on the falling edge of an input to the PDB can be programmed independently of the rising edge. This allows the user to program the length of the pulse outputted from the PDB. Thus, for instance, the width of the pulse from the Watchdog Fault Detector can be adjusted, or the user can ensure that a supply supervised by one of the SFD's is within its UV/OV range for a programmed period of time before asserting a PDO. A delay of between 0ms and 500ms can be programmed in the PnPDBTIM registers. 4 bits each are used to program the rising edge and falling edge. Once programmed, the PDB operates as follows. If the user programs a delay on the rising edge of, say, 200ms, the PDB looks for a rising edge on the input. Once it sees the edge it starts a timer. If the input remains high and the timer reaches 200ms, then the PDB immediately outputs a rising edge. If the input falls low before the timer has reached 200ms then no edge is outputted from the PDB and the timer is reset. Because there is separate control over the falling edge, if no delay is programmed on the falling edge, the delay defaults to 0 and a falling edge on the input will immediately appear on the output. If a falling edge delay is programmed, then the PDB operates exactly the opposite to the way it does for a rising edge. Again, if a delay of, say, 200ms is programmed on the falling edge, the PDB looks for a falling edge on the input. Once it sees the edge, it again starts a timer. If the input remains low and the timer reaches 200ms, then the output transitions from high to low. A valid rising edge must appear at the output before a falling edge delay can be activated. The function of the PDB is illustrated in figure 6 below. Aside from the extra timing flexibility offered, the programmable delay also provides a crude form of filtering. In much the same way as the Glitch Filter operates, an input must be high (or low) for a programmed period of time before being seen on the output. Transients which are shorter that the programmed timeouts will not appear on the output. The bitmap for the register which controls both the rising and falling edges is shown overleaf:PROGRAMMED RISETIME ADM1060 PDB INPUT PROGRAMMED FALLTIME =0 PROGRAMMED RISETIME T0 TRISE T0 TRISE TFALL T0 TRISE T0 TRISE TFALL PDB OUTPUT PROGRAMMING RISE TIME ONLY PDB INPUT PROGRAMMED RISETIME PROGRAMMED FALLTIME PROGRAMMED RISETIME PROGRAMMED FALLTIME T0 TRISE T1 TFALL T0 TRISE T1 TFALL T0 TRISE T1 TFALL T0 TRISE T1 TFALL PDB OUTPUT PROGRAMMING RISE TIME AND FALL TIME Figure 6. Functionality of the Programmable Delay Block (PDB) REV. PrJ 11/02 -27- PRELIMINARY TECHNICAL DATA ADM1060 TABLE 36. LIST OF REGISTERS FOR PROGRAMMABLE DELAY BLOCK (PDB) Hex Addr. 0C 1C 2C 3C 4C 5C 6C 7C 8C Table Name Default Power On Value 00h 00h 00h 00h 00h 00h 00h 00h 00h Description ADM1060 LOGIC 37 37 37 37 37 37 37 37 37 P1PDBTIM P2PDBTIM P3PDBTIM P4PDBTIM P5PDBTIM P6PDBTIM P7PDBTIM P8PDBTIM P9PDBTIM Delay for PDB1. Delay for rising edge and falling edge pro grammed separately. Delay for PDB2. Delay for rising edge and falling edge pro grammed separately. Delay for PDB3. Delay for rising edge and falling edge prog rammed separately. Delay for PDB4. Delay for rising edge and falling edge pro grammed separately. Delay for PDB5. Delay for rising edge and falling edge pro grammed separately. Delay for PDB6. Delay for rising edge and falling edge pro grammed separately. Delay for PDB7. Delay for rising edge and falling edge pro grammed separately. Delay for PDB8. Delay for rising edge and falling edge pro grammed separately. Delay for PDB9. Delay for rising edge and falling edge pro grammed separately. TABLE 37. PnPDBTIM REGISTERS 0Ch,1CH,2CH,3CH,4CH,5CH,6CH,7CH,8CH Bit 7-4 3-0 Name TR3-TR0 TF3-TF0 R/W W W Description Programmed Rise Time Programmed Fall Time TR3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 TF3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 TR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 TF2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 TR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 TF1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 TR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 TF0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Delay(ms) 0 1 2 5 10 20 40 60 80 100 150 200 250 300 400 500 Delay(ms) 0 1 2 5 10 20 40 60 80 100 150 200 250 300 400 500 -28- REV. PrJ 11/02 PRELIMINARY TECHNICAL DATA ADM1060 OUTPUTS PROGRAMMABLE DRIVER OUTPUTS ADM1060 the user to directly drive the gate of an N- Channel FET in the path of a power supply. The required pull- up is selected by programming bits 0 to 3 in PnPDOCFG appropriately (see table overleaf). The data driving each of the PDO's can come from one of 3 inputs. These inputs are enabled by a bit each in the PnPDOCFG registers. The inputs are:- The ADM1060 has 9 Programmable Driver Outputs (PDO's). These are the logic outputs of the device. Each PDO is normally controlled by a PDB. Thus, the PDO's can be set up assert when the conditions on the PDB are met (eg) the SFD's are in tolerance, the levels on the GPI are correct, the Watchdog timer has not timed out etc. The PDO's can be used for a number of functions (eg) provide a POWER_GOOD signal when all the SFD's are in tolerance, provide a reset generator output if one of the SFD's goes out of spec. (which can be used as a status signal for a DSP or other microprocessor), provide enable signals for LDO's on the supplies that the ADM1060 is supervising etc. There are a number of pull up options on the PDO's to enable the user to program the output level. The outputs can be programmed to be:* Open Drain (allows the user to connect an external * * * * * * The (delayed) output from the associated PLB (enabled by setting bit CFG4 to 1) Data which is driven directly over the SMBus interface (enabled by setting bit CFG5 to1). When set in this mode, the data from the PDB is disabled and the data on the PDO is the data on CFG4. Thus the PDO can be software controlled (eg) to initiate a software power up/ powerdown. * pull- up resistor) Open Drain with weak internal pull-up to VDD Open Drain with strong internal pull-up to VDD Open Drain with weak internal pull-up to VP_n Open Drain with strong internal pull-up to VP_n Internally charge-pumped high drive (+12V) * An On- Chip Clock (enabled by setting bit CFG6 to1). A 100KHz clock is available to clock an external device (eg) a LED. More detail of these data modes is given in the register map overleaf. The default setup of each of the PDO's is to be pulled low by a weak (20k ) pulldown resistor. This is also the setup of the PDO's on power- up until the registers are loaded and the programmed conditions are latched. The outputs are actively pulled low once 1V or greater is seen at any of VPn or VH. Until there is a 1V supply on the chip the outputs are high impedance. This provides a known condition for the PDO's during power- up. The pulldown can be overdriven if required (eg) tie an external pull- up resistor to the PDO to ensure that the gate of a PMOS device was not turned on. The register list and the bit map for the PDO's is shown below. The last option is only available on PDO1- 4. This allows VFET (PDO1-4 ONLY) VDD CFG4 CFG5 CFG6 VP4 SEL VP1 10V 20kV PDB_OUT CFG4 M_CLK 10V 20kV 10V 20kV PDO Figure 7. Programmable Driver Output REV. PrJ 11/02 -29- 20kV PRELIMINARY TECHNICAL DATA ADM1060 Hex Address 0D Table Name Default Power On Value 00h Description ADM1060 OUTPUTS TABLE 38. LIST OF REGISTERS FOR THE PROGRAMMABLE DRIVER OUTPUTS 39 P1PDOCFG Selects the format of the PDO1 output (open drain, open drain with internal pull-up, charge pumped etc.) Selects the format of the PDO2 output (open drain, open drain with internal pull-up, charge pumped etc.) Selects the format of the PDO3 output (open drain, open drain with internal pull-up, charge pumped etc.) Selects the format of the PDO4 output (open drain, open drain with internal pull-up, charge pumped etc.) Selects the format of the PDO5 output (open drain, open drain with internal pull-up etc.). Note: Charge Pumped output is not available on this driver 1D 39 P2PDOCFG 00h 2D 39 P3PDOCFG 00h 3D 39 P4PDOCFG 00h 4D 39 P5PDOCFG 00h 5D 39 P6PDOCFG 00h Selects the format of the PDO6 output (open drain, open drain with internal pull-up etc.). Note: Charge Pumped output is not available on this driver 6D 39 P7PDOCFG 00h Selects the format of the PDO7 output (open drain, open drain with internal pull-up etc.). Note: Charge Pumped output is not available on this driver 7D 39 P8PDOCFG 00h Selects the format of the PDO8 output (open drain, open drain with internal pull-up etc.). Note: Charge Pumped output is not available on this driver 8D 39 P9PDOCFG 00h Selects the format of the PDO9 output (open drain, open drain with internal pull-up etc.). Note: Charge Pumped output is not available on this driver TABLE 39. REGISTER 0DH,1DH,2DH,3DH,4DH,5DH,6DH,7DH,8DH Bit 7 6-4 Name Reserved CFG6-CFG4 R/W N/A R/W Description Cannot be used PnPDOCFG (POWER- ON DEFAULT 00H) Control the logical state of the PDO. These three bits deter mine what effect, if any, the logical input to the PDO has on its output CFG6 0 0 0 0 1 CFG5 0 0 1 1 X CFG4 0 1 0 1 X PDO 0 PLB_OUT 0 1 MCLK State Disabled, with weak pull-down Enabled, follows PLB Logic Output Enable SMBus Data, Drive Low Enable SMBus Data, Drive High Enable MCLK out onto pin 3-0 CFG3-CFG0 R/W CFG3 0 0 0 0 0 0 1 1 1 1 1 1 CFG2 0 0 1 1 1 1 0 0 0 0 1 1 CFG1 0 1 0 0 1 1 0 0 1 1 1 1 CFG0 X X 0 1 0 1 0 1 0 1 0 1 Pull-Up Supply none VCP VP1 VP1 VP2 VP2 VP3 VP3 VP4 VP4 VDD VDD Pull-Up Strength N/A (1/fC) Low High Low High Low High Low High Low High -30- REV. PrJ 11/02 PRELIMINARY TECHNICAL DATA ADM1060 STATUS/FAULTS FAULT/STATUS REPORTING ON THE ADM1060 ADM1060 The important exception is the MSB of the LATF1 register. This is the ANYFLT bit. This bit goes high if one of the other bits in the 2 registers "faults". A "fault" is defined as a change in polarity from the last time the fault registers were read. Once ANYFLT goes high the contents of the 2 registers are latched, thus preventing more than 1 of the other bits from changing polarity before the contents of the registers are read. The first faulting input can, therefore, be determined. The sequence in which the registers are read is determined by ANYFLT. As long as ANYFLT remains at 0, only the contents of LATF1 are read. There are 2 reasons for this. The first is that ANYFLT=0 implies that no fault has occurred and, therefore, there is no need to read the contents of LATF2. Secondly, and more importantly, reading register LATF2 actually resets the ANYFLT bit to 0. Thus, if a fault occurred on an SFD after LATF1 had been read but before LATF2 had been read, ANYFLT would change to 1, indicating that a fault had occurred, but would be reset to 0 once LATF2 was read, thus erasing the log of the fault. In summary then, LATF2 should only ever be read if ANYFLT=1. Reading the registers in this sequence ensures that the contents are never reset before a fault has been logged over the SMBus, thus ensuring that the supervising processor or CPLD knows what function supervised by the ADM1060 caused the fault. The "faulting" function is determined by comparing the contents of the fault plane (ie) the contents of the 2 registers, with the values read previously, and determining which bit changed polarity. The functionality of the Fault Plane is best illustrated with an example. Take, for instance, VP1 to have an input supply of 5.0V. A UV/OV window of 4.5V to 5.5V is set up on VP1. The supply is ramped in and out of this window, each time reading the contents of LATF1 and LATF2. The values recorded are as follows:1. VP1 at 5V- LATF1=LATF2=00000000. This is expected. The supply is in tolerance, SFD output is 0, therefore no fault. 2. VP1 at 4.2V- LATF1=10001000, LATF2=00000000. SFD output has changed status to 1, therefore ANYFLT goes high. 3. VP1 at 5.0V- LATF1=10000000, LATF2=00000000. SFD output has changed status to 0, therefore ANYFLT goes high again. 4. VP1 at 5.8V- LATF1=10001000, LATF2=00000000. SFD output again changed status from 0 to 1, so ANYFLT goes high. 5.VP1 at 4.2V- LATF1=10000000, LATF2=00000000. At first glance, this would appear to be incorrect, since SFD output should be at 1 (4.2V is an undervoltage fault). However, in ramping down from 5.8V to 4.2V, the supply passed into the UV/OV window, the SFD output changed status from 1 to 0, ANYFLT was set high and the register contents were latched. It is these values which were read before being reset by reading LATF2. There are also two mask registers provided, which enable the user to ignore a fault on a given function. The bits of the error mask registers are mapped in the same way as As discussed in the last section, any one, a number or all of the PDO's can be programmed to assert under a set of pre- programmed conditons. These conditions could be a fault on a SFD, a change in status on a GPI, a timeout on the watchdog detector etc. Because of the flexibility and the choice of combinations available on the ADM1060, the assertion of the PDO will tell the user nothing about what caused it to assert (unless it is programmed to assert with only one input). To enable the user to debug the cause of the PDO assertion, a number of registers are provided on the ADM1060 which provide status and fault information on the various individual functions supervised by the device. STATUS REGISTERS A number of Status Registers are provided which indicate the logic state of all of the functions controlled by the ADM1060. These logics states include the output of both the UV and OV comparators of each of the 7 SFD's, the logic output of the SFD's themselves, the logic state of the GPI's, the error condition on the WDI, and the logic state of each of the 9 PDO's. The contents of these registers can be read at any time via the SMBus interface. The content of these registers is read- only. The register and bitmap for each of these status registers is described in the table overleaf. FAULT REGISTERS Fault reporting is also provided on the ADM1060. If a fault occurs, causing, say, a PDO to change its status, the user can determine what function actually faulted. This is achieved by providing a "fault plane", consisting of 2 registers, LATF1 and LATF2, which the system controller can read out of the ADM1060 via the SMBus. Each bit in the 2 registers (with one important exception, see below) is assigned to one of the inputs of the devices as shown in the table below:REGISTER LATF1 BIT 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 ASSIGNED FUNCTION ANYFLT Logic Output of VP4's SFD Logic Output of VP3's SFD Logic Output of VP2's SFD Logic Output of VP1's SFD Logic Output of VH's SFD Logic Output of VB2's SFD Logic Output of VB1's SFD Logic Output of WDI Logic Input on GPI4 Logic Input on GPI3 Logic Input on GPI2 Logic Input on GPI1 LATF2 Table 25. Fault Plane of ADM1060 Each bit represents the logical status of its assigned function (ie) the logical output of the SFD's and WDI and the logic level on the GPI inputs. REV. PrJ 11/02 -31- PRELIMINARY TECHNICAL DATA ADM1060 those of the fault registers with the exception that the ANYFLT bit cannot be masked. Setting a 1 in the error mask register results in the equivalent bit in the fault register always remaining at 0, regardless of whether there is a fault on that function or not. The register and bit maps for both the fault and error mask registers are shown below. ADM1060 STATUS/FAULTS STATUS REGISTERS TABLE 40. LIST OF STATUS REGISTERS Hex Addr. D8 D9 DA DB DE DF Table Name Default Power On Value 00h 00h 00h 00h 00h 00h Description 41 42 43 44 45 46 UVSTAT OVSTAT SFDSTAT GWSTAT PDOSTAT1 PDOSTAT2 Logic output of the UV comparator on each of the 7 SFD's Logic output of the OV comparator on each of the 7 SFD's Logic output (post Fault Type block) on each of the 7 SFD's Logic state of the 4 GPI's and the Watchdog Fault Detector Logic output of PDO's 1 to 8 Logic output of PDO 9 TABLE 41. BIT MAP FOR UVSTAT REGISTER D8H (POWER- ON DEFAULT 00H) Bit 7 6 5 4 3 2 1 0 Name Reserved VP4UV VP3UV VP2UV VP1UV VHUV VB2UV VB1UV R/W N/A R R R R R R R Description Cannot be used If high, then voltage on VP4 input is lower than the UV threshold If high, then voltage on VP3 input is lower than the UV threshold If high, then voltage on VP2 input is lower than the UV threshold If high, then voltage on VP1 input is lower than the UV threshold If high, then voltage on VH input is lower than the UV threshold If high, then voltage on VB2 input is lower than the UV threshold If high, then voltage on VB1 input is lower than the UV threshold TABLE 42. BIT MAP FOR OVSTAT REGISTER D9H (POWER- ON DEFAULT 00H) Bit 7 6 5 4 3 2 1 0 Name Reserved VP4OV VP3OV VP2OV VP1OV VHOV VB2OV VB1OV R/W N/A R R R R R R R Description Cannot be used If high, then voltage on VP4 input is higher than the OV threshold If high, then voltage on VP3 input is higher than the OV threshold If high, then voltage on VP2 input is higher than the OV threshold If high, then voltage on VP1 input is higher than the OV threshold If high, then voltage on VH input is higher than the OV threshold If high, then voltage on VB2 input is higher than the OV threshold If high, then voltage on VB1 input is higher than the OV threshold -32- REV. PrJ 11/02 PRELIMINARY TECHNICAL DATA ADM1060 STATUS/FAULTS TABLE 43. BIT MAP FOR SFDSTAT REGISTER DAH (POWER- ON DEFAULT 00H) Bit 7 6 5 4 3 2 1 0 Name Reserved VP4FLT VP3FLT VP2FLT VP1FLT VHFLT VB2FLT VB1FLT R/W N/A R R R R R R R Description Cannot be used If high, then fault (UV, OV or Out- of- Window) has occurred on VP4 input If high, then fault (UV, OV or Out- of- Window) has occurred on VP3 input If high, then fault (UV, OV or Out- of- Window) has occurred on VP2 input If high, then fault (UV, OV or Out- of- Window) has occurred on VP1 input If high, then fault (UV, OV or Out- of- Window) has occurred on VH input If high, then fault (UV, OV or Out- of- Window) has occurred on VB2 input If high, then fault (UV, OV or Out- of- Window) has occurred on VB1 input ADM1060 TABLE 44. BIT MAP FOR GWSTAT REGISTER DBH (POWER- ON DEFAULT 00H) Bit 7-5 4 3 2 1 0 Name Reserved WDISTAT GPI4STAT GPI3STAT GPI2STAT GPI1STAT R/W N/A R R R R R Description Cannot be used If high, then timeout has elapsed on the Watchdog Detector Logic level currently being driven on GPI4 input Logic level currently being driven on GPI3 input Logic level currently being driven on GPI2 input Logic level currently being driven on GPI1 input TABLE 45. BIT MAP FOR PDOSTAT1 REGISTER DEH (POWER- ON DEFAULT 00H) Bit 7 6 5 4 3 2 1 0 Name PDO8STAT PDO7STAT PDO6STAT PDO5STAT PDO4STAT PDO3STAT PDO2STAT PDO1STAT R/W R R R R R R R R Description Logic level currently being driven on PDO8 output Logic level currently being driven on PDO7 output Logic level currently being driven on PDO6 output Logic level currently being driven on PDO5 output Logic level currently being driven on PDO4 output Logic level currently being driven on PDO3 output Logic level currently being driven on PDO2 output Logic level currently being driven on PDO1 output TABLE 46. BIT MAP FOR PDOSTAT2 REGISTER DFH (POWER- ON DEFAULT 00H) Bit 7-1 0 Name Reserved PDO9STAT R/W N/A R Description Cannot be used Logic level currently being driven on PDO9 output REV. PrJ 11/02 -33- PRELIMINARY TECHNICAL DATA ADM1060 FAULT REGISTERS TABLE 47. LIST OF FAULT REGISTERS Hex Addr. DC DD Table Name Default Power On Value 00h 00h Description ADM1060 STATUS/FAULTS 48 49 LATF1 LATF2 Fault Status Register for the 7 SFD's Fault Status Register for the 4 GPI's and the Watchdog Detector TABLE 48. BIT MAP FOR LATF1 REGISTER DCH (POWER- ON DEFAULT 00H) Bit 7 tions 6 5 4 3 2 1 0 VP4FLT VP3FLT VP2FLT VP1FLT VHFLT VB2FLT VB1FLT R R R R R R R Name ANYFLT R/W R Description If high, then a change in logic status (fault) has been logged on one of the 12 funcmonitored since the last time the Fault Registers were read. If high, then a fault has occurred on supply at input VP4 If high, then a fault has occurred on supply at input VP3 If high, then a fault has occurred on supply at input VP2 If high, then a fault has occurred on supply at input VP1 If high, then a fault has occurred on supply at input VH If high, then a fault has occurred on supply at input VB2 If high, then a fault has occurred on supply at input VB1 TABLE 49. BIT MAP FOR LATF2 REGISTER DDH (POWER- ON DEFAULT 00H) Bit 7-5 4 Name Reserved WDFLT R/W N/A R Description Cannot be used If high, then the logic level on the WDI output has changed since the last time that the fault registers were read If high, then the logic level on GPI4 input has changed since the last time that the fault registers were read If high, then the logic level on GPI3 input has changed since the last time that the fault registers were read If high, then the logic level on GPI2 input has changed since the last time that the fault registers were read If high, then the logic level on GPI1 input has changed since the last time that the fault registers were read 3 GPI4FLT R 2 GPI3FLT R 1 GPI2FLT R 0 GPI1FLT R -34- REV. PrJ 11/02 PRELIMINARY TECHNICAL DATA ADM1060 STATUS/FAULTS MASK REGISTERS TABLE 50. LIST OF MASK REGISTERS Hex Addr. 9D 9E Table Name Default Power On Value 00h 00h Description ADM1060 51 52 ERRMASK1 ERRMASK2 Error Mask Register for the 7 SFD's Error Mask Register for the 4 GPI's and the Watchdog Detector TABLE 51. BIT MAP FOR ERRMASK1 REGISTER 9DH (POWER- ON DEFAULT 00H) Bit 7 6 5 4 3 2 1 0 Name Reserved VP4MASK VP3MASK VP2MASK VP1MASK VHMASK VB2MASK VB1MASK R/W X R/W R/W R/W R/W R/W R/W R/W Description Unused If high, then a fault occurring on the supply at input VP4 is ignored, and not logged in LATF1 If high, then a fault occurring on the supply at input VP3 is ignored, and not logged in LATF1 If high, then a fault occurring on the supply at input VP2 is ignored, and not logged in LATF1 If high, then a fault occurring on the supply at input VP1 is ignored, and not logged in LATF1 If high, then a fault occurring on the supply at input VH is ignored, and not logged in LATF1 If high, then a fault occurring on the supply at input VB2 is ignored, and not logged in LATF1 If high, then a fault occurring on the supply at input VB1 is ignored, and not logged in LATF1 TABLE 52. BIT MAP FOR ERRMASK2 REGISTER 9EH (POWER- ON DEFAULT 00H) Bit 7-5 4 3 2 1 0 Name Reserved WDIMASK GPI4MASK GPI3MASK GPI2MASK GPI1MASK R/W X R/W R/W R/W R/W R/W Description Unused If high, then a change in the logic level on the WDI output is ignored, and not logged in LATF2 If high, then a change in the logic level on the GPI4 input is ignored, and not logged in LATF2 If high, then a change in the logic level on the GPI3 input is ignored, and not logged in LATF2 If high, then a change in the logic level on the GPI2 input is ignored, and not logged in LATF2 If high, then a change in the logic level on the GPI1 input is ignored, and not logged in LATF2 REV. PrJ 11/02 -35- PRELIMINARY TECHNICAL DATA ADM1060 CONFIGURATION DOWNLOAD AT POWER- UP PROGRAMMING ADM1060 in the original setup until the instruction is given to change. The instruction to download from the EEPROM in option 3 above is also a useful way to restore the original EEPROM contents if revisions to the configuration are unsatisfactory to the user and they wish the ADM1060 to return to a known operating mode. This type of operation is possible because of the topology of the ADM1060. The Local (volatile) registers, or RAM, are all double buffered latches. Setting bit 0 of the UPDCFG register to 1 leaves the double buffered latches open at all times. If bit 0 is set to 0, then when RAM write occurs across the SMBus only the first side of the double buffered latch is written to. The user must then write a 1 to bit 1 of the UPDCFG register. This generates a pulse to update all of the second latches at once. Similarly with EEPROM writes. A final bit in this register is used to enable EEPROM page erasure. If this bit is set high, then the contents of an EEPROM page can all be set to 0. If low, then the contents of a page cannot be erased, even if the command code for page erasure is programmed across the SMBus. The bitmap for register UPDCFG is shown below. A flow chart for download at power up and subsequent configuration updates is shown overleaf:- The configuration of the ADM1060- the UV/OV thresholds, glitch filter timeouts, PLB combinations, PDO pullups etc, is dictated by the contents of the RAM. The RAM is comprised of local latches which set the configuration. These latches are double buffered and are actually comprised of 2 identical latches (Latch A and Latch B). An update of the double- buffered latch updates Latch A first then Latch B. The advantage of this architecture is explained below. These latches are volatile memory and lose their contents at power- down. Therefore, at powerup the configuration in the RAM must be restored. This is achieved by downoading the contents of the EEPROM (non- volatile memory) to the local latches. This download occurs in a number of steps. 1. With no power applied to the device, the PDO's are all high impedance. 2. Once 1V appears on any of the inputs connected to the VDD Arbitrator (VH or VPn), the PDO's are all (weakly) pulled to GND. 3. Once the supply rises above the Undervoltage Lockout of the device (UVLO is 2.5V), the EEPROM starts to download to the RAM. 4. The EEPROM downloads its contents to all Latch A's. 5. Once the contents of the EEPROM are completely downloaded, the device controller outputs a control pulse enabling all Latch A's to download to all Latch B's, thus completing the configuration download. Any attempt to communicate with the device prior to this download completion will result in a NACK being issued from the ADM1060. UPDATING THE CONFIGURATION OF THE ADM1060 Once powered up, with all of the configuration settings loaded from EEPROM into the RAM registers, the user may wish to alter the configuration of functions on the ADM1060 (eg) change the UV or OV limit of an SFD, change the fault output of an SFD, change the timeout of the Watchdog Detector, change the rise time delay of one of the PDO's etc. The ADM1060 provides a number of options which allow the user to update the configuration differently over the SMBus interface. All of these options are controlled in the register UPDCFG. The options are:1. Update the configuration in real time. The user writes to RAM across the SMBus and the configuration is updated immediately. 2. Update A Latches "offline" and then update all B Latches at the same time. With this method, the configuration of the ADM1060 will remain unchanged and continue to operate in the original setup until the instruction is given to update the B Latches. 3. Change EEPROM register contents "offline" and then download the revised EEPROM contents to the RAM registers. Again, with this method, the configuration of the ADM1060 will remain unchanged and continue to operate -36- REV. PrJ 11/02 PRELIMINARY TECHNICAL DATA PROGRAMMING ADM1060 TABLE 52. LIST OF CONFIGURATION UPDATE REGISTERS Hex Addr. 90 Table Name Default Power On Value 00h Description ADM1060 53 UPDCFG Configuration Update Control register for changing configuration of the ADM1060 after power- up TABLE 53. BIT MAP FOR UPDCFG REGISTER 90H (POWER- ON DEFAULT 00H) Bit 7-4 3 2 Name Reserved EE_ERASE EEPROMLD R/W N/A R/W W Description Cannot be used If set high, then EEPROM page erasure can be programmed. If set high, the ADM1060 will download the contents of its EEPROM to the RAM registers. This bit self clears (returns to 0) after the download If set high, the ADM1060 will download the buffered RAM register data into the local latches. This bit self clears (returns to 0) after the download If set high, the ADM1060 will update its configuration in real time as a word is written to a local RAM register via the SMBus 1 RAMLD W 0 UPD R/W SMBus DEVICE CONTROLLER POWER- UP (Vcc >2.5V) E E P R O M L D R A M L D D A T A LATCH A U P D EEPROM LATCH B FUNCTION (eg) O V T hreshold on VP1 Figure 8. Configuration Update Flow Diagram REV. PrJ 11/02 -37- PRELIMINARY TECHNICAL DATA ADM1060 INTERNAL REGISTERS OF THE ADM1060 PROGRAMMING ADM1060 SERIAL BUS INTERFACE The ADM1060 contains a large number of data registers. A brief description of the principal registers is given below. More detailed descriptions are given in the relevant sections of the data sheet. Address Pointer Register: This register contains the address that selects one of the other internal registers. When writing to the ADM1060, the first byte of data is always a register address, which is written to the Address Pointer Register. Configuration Registers: Provide control and configuration for various operating parameters of the ADM1060. Polarity Registers: These registers define the polarity of inputs to the PLBA Mask Registers: Allow masking of individual inputs to the PLBA and also masking of faults in the fault reporting registers. EEPROM Control of the ADM1060 is carried out via the serial System Management Bus (SMBus). The ADM1060 is connected to this bus as a slave device, under the control of a master device. It takes approximately 2ms after power up for the ADM1060 to download from it's EEPROM. Therefore access is restricted to the ADM1060 until the download is completed. IDENTIFYING THE ADM1060 ON THE SMBUS The ADM1060 has 512 bytes of non-volatile, ElectricallyErasable Programmable Read-Only Memory (EEPROM), from register addresses F800h to F9FFh. This may be used for permanent storage of data that will not be lost when the ADM1060 is powered down, unlike the data in the volatile registers. Although referred to as Read Only Memory, the EEPROM can be written to (as well as read from) via the serial bus in exactly the same way as the other registers. The only major differences between the E2PROM and other registers are: 1. An EEPROM location must be blank before it can be written to. If it contains data, it must first be erased. 2. Writing to EEPROM is slower than writing to RAM. 3. Writing to the EEPROM should be restricted because it has a limited write/cycle life of typically 10,000 write operations, due to the usual EEPROM wear-out mechanisms. The EEPROM is split into 16 (0 to 15) pages of 32 Bytes each. Pages 0 to 6, starting at address F800, hold the configuration data for the applications on the ADM1060 (the PLB, SFD's, GPI's, WDI, PDO's etc.). These EEPROM addresses are the same as the RAM register addresses, prefixed by F8. Page 7 is reserved. Pages 8 to 15 are for customer use. Data can be downloaded from EEPROM to RAM in one of 2 ways:1. At Power- up, pages 0 to 6 are downloaded. 2. Setting bit 2 of the UPDCFG Register (90h) performs a user download of pages 0 to 6. The ADM1060 has a 7-bit serial bus slave address. When the device is powered up, it will do so with a default serial bus address. The five MSB's of the address are set to 10101, the two LSB's are determined by the logical states of pin A1 and A0. This allows the connection of 4 ADM1060's to the one SMBus. The device also has a number of identification registers (read only) which can be read across the SMBus. These are:Name Address Value Function MANID 93h 41h Manufacturer ID for Analog Devices DEVID 94h 3Eh Device ID REVID 95h --h Silicon Revision MARK1 96h --h S/w brand MARK2 97h --h S/w brand GENERAL SMBUS TIMING Figures 8a and 8b show timing diagrams for general read and write operations using the SMBus. The SMBus specification defines specific conditions for different types of read and write operation, which are discussed later. The general SMBus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, defined as a high to low transition on the serial data line SDA whilst the serial clock line SCL remains high. This indicates that a data stream will follow. All slave peripherals connected to the serial bus respond to the START condition, and shift in the next 8 bits, consisting of a 7-bit slave address (MSB first) plus a R/W bit, which determines the direction of the data transfer, i.e. whether data will be written to or read from the slave device (0 = write, 1 = read). The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the Acknowledge Bit, and holding it low during the high period of this clock pulse. All other devices on the bus now remain idle whilst the selected device waits for data to be read from or written to it. If the R/W bit is a 0 then the master will write to the slave device. If the R/W bit is a 1 the master will read from the slave device. 2. Data is sent over the serial bus in sequences of 9 clock pulses, 8 bits of data followed by an Acknowledge Bit from the slave device. Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low to high transition when the clock is high may be interpreted as a STOP signal. -38- REV. PrJ 11/02 PRELIMINARY TECHNICAL DATA PROGRAMMING ADM1060 If the operation is a write operation, the first data byte after the slave address is a command byte. This tells the slave device what to expect next. It may be an instruction such as telling the slave device to expect a block write, or it may simply be a register address that tells the slave where subsequent data is to be written. Since data can flow in only one direction as defined by the R/W bit, it is not possible to send a command to a slave device during a read operation. Before doing a read operation, it may first be necessary to do a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. 3. When all data bytes have been read or written, stop conditions are established. In WRITE mode, the master will pull the data line high during the 10th clock pulse 1 SCL 9 1 9 ADM1060 to assert a STOP condition. In READ mode, the master device will release the SDA line during the low period before the 9th clock pulse, but the slave device will not pull it low. This is known as No Acknowledge. The master will then take the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a STOP condition. SDA START BY MASTER 0 1 0 1 1 A1 A0 R/W ACK. BY SLAVE D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY SLAVE FRAME 1 SLAVE ADDRESS 1 SCL (CONTINUED ) SDA (CONTINUED ) D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY SLAVE FRAME 3 DATA BYTE D7 9 1 FRAME 2 COMMAND CODE 9 D6 D5 D4 D3 D2 D1 D0 ACK. BY SLAVE STOP BY MASTER FRAME N DATA BYTE Figure 8a. General SMBus Write Timing Diagram 1 SCL 9 1 9 SDA START BY MASTER 0 1 0 1 1 A1 A0 R/W ACK. BY SLAVE D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY MASTER FRAME 1 SLAVE ADDRESS 1 SCL (CONTINUED ) SDA (CONTINUED ) D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY MASTER FRAME 3 DATA BYTE D7 D6 9 1 FRAME 2 DATA BYTE 9 D5 D4 D3 D2 D1 D0 NO ACK. STOP BY MASTER FRAME N DATA BYTE Figure 8b. General SMBus Read Timing Diagram tR tLO W tF tHD;ST A SCL tHIG tHD;ST A tHD;DA T tSU;STA tSU;DA T tSU;ST O H SDA tBUF P S S P Figure 8c. Diagram for Serial Bus Timing REV. PrJ 11/02 -39- PRELIMINARY TECHNICAL DATA ADM1060 SMBUS PROTOCOLS FOR RAM AND EEPROM PROGRAMMING ADM1060 3. Erase a page of EEPROM memory. EEPROM memory can be written to only if it is unprogrammed. Before writing to one or more EEPROM memory locations that are already programmed, the page or pages containing those locations must first be erased. EEPROM memory is erased by writing a command byte. The master sends a command code that tells the slave device to erase the page. The ADM1060 command code for a pages(s) erasure is FEh (11111110). Note that, in order for page erasure to take place, the page address has to be given in the previous write word transaction (see write byte below). Also, bit 3 in register UPDCFG (address 90h) must be set to 1. 1 2 3 4 COMMAND BYTE (FEh) 5 6 The ADM1060 contains volatile registers (RAM) and non-volatile EEPROM. User RAM occupies address locations from 00h to DFh, whilst EEPROM occupies addresses from F800h to F9FFh. Data can be written to and read from both RAM and EEPROM as single data bytes. Data can only be written to unprogrammed EEPROM locations. To write new data to a programmed location it is first necessary to erase it. EEPROM erasure cannot be done at the byte level, the EEPROM is arranged as 16 pages of 32 bytes, and an entire page must be erased. Page erasure is enabled by setting bit 3 in register UPDCFG (address 90h) to 1. If this is not set then page erasure cannot occur, even if the command byte (FEh) is programmed across the SMBus. ADM1060 WRITE OPERATIONS SLAVE S WA ADDRESS AP Figure 9b. EEPROM Page Erasure The SMBus specification defines several protocols for different types of read and write operations. The ones used in the ADM1060 are discussed below. The following abbreviations are used in the diagrams: S P R W A A START STOP READ WRITE ACKNOWLEDGE NO ACKNOWLEDGE As soon as the ADM1060 receives the command byte, page erasure begins. The master device can send a STOP command as soon as it sends the command byte. Page erasure takes approximately 20ms. If the ADM1060 is accessed before erasure is complete, it will respond with No Acknowledge. Write Byte/Word In this operation the master device sends a command byte and one or two data bytes to the slave device, as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 5. The slave asserts ACK on SDA. 6. The master sends a data byte. 7. The slave asserts ACK on SDA. 8. The master sends a data byte (or may assert STOP at this point). 9. The slave asserts ACK on SDA. 10.The master asserts a STOP condition on SDA to end the transaction. In the ADM1060, the write byte/word protocol is used for three purposes. 1. Write a single byte of data to RAM. In this case the command byte is the RAM address from 00h to DFh and the (only) data byte is the actual data. This is illustrated in Figure 9c. 1 2 3 4 5 6 78 The ADM1060 uses the following SMBus write protocols: Send Byte In this operation the master device sends a single command byte to a slave device, as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 5. The slave asserts ACK on SDA. 6. The master asserts a STOP condition on SDA and the transaction ends. In the ADM1060, the send byte protocol is used for two purposes. 1. To write a register address to RAM for a subsequent single byte read from the same address or block read or write starting at that address. This is illustrated in Figure 9a. 1 S 2 3 4 5 6 RAM ADDRESS A P (00h TO DFh) SLAVE WA ADDRESS SLAVE S WA ADDRESS RAM ADDRESS A DATA A P (00h TO DFh) Figure 9a. Setting A RAM Address For Subsequent Read Figure 9c. Single Byte Write To RAM 2. Set up a two byte EEPROM address for a subsequent read, write, block read, block write or page erase. In -40- REV. PrJ 11/02 PRELIMINARY TECHNICAL DATA PROGRAMMING ADM1060 this case the command byte is the high byte of the EEPROM address from F8h to F9h. The (only) data byte is the low byte of the EEPROM address. This is illustrated in Figure 9c. 1 2 3 4 5 6 7 8 ADM1060 Unlike some EEPROM devices which limit block writes to within a page boundary, there is no limitation on the start address when performing a block write to EEPROM, except: 1. There must be at least N locations from the start address to the highest EEPROM address (F9FFh), to avoiding writing to invalid addresses. 2. If the addresses cross a page boundary, both pages must be erased before programming. Note that the ADM1060 features a clock extend function for writes to EEPROM. Programming an EEPROM byte takes approximately 250s, which would limit the SMBus clock for repeated or block write operations. The ADM1060 pulls SCL low and extends the clock pulse when it cannot accept any more data. ADM1060 READ OPERATIONS EEPROM EEPROM ADDRESS ADDRESS SLAVE A AP S WA LOW BYTE HIGH BYTE ADDRESS (00h TO FFh) (F8h TO F9h) Figure 9d. Setting An EEPROM Address Note for page erasure that as a page consists of 32 bytes only the three MSB's of the address low byte are important. The lower 5 bits of the EEPROM address low byte only specify addresses within a page and are ignored during an erase operation. 3. Write a single byte of data to EEPROM. In this case the command byte is the high byte of the EEPROM address from F8h to F9h. The first data byte is the low byte of the EEPROM address and the second data byte is the actual data. This is illustrated in Figure 9e. 1 2 3 4 5 6 7 8 9 10 EEPROM EEPROM ADDRESS ADDRESS SLAVE A A DATA A P S WA LOW BYTE HIGH BYTE ADDRESS (00h TO FFh) (F8h TO F9h) The ADM1060 uses the following SMBus read protocols: RECEIVE BYTE In this operation the master device receives a single byte from a slave device, as follows: 1.The master device asserts a START condition on SDA. 2.The master sends the 7-bit slave address followed by the read bit (high). 3.The addressed slave device asserts ACK on SDA. 4.The master receives a data byte. 5.The master asserts NO ACK on SDA. 6.The master asserts a STOP condition on SDA and the transaction ends. In the ADM1060, the receive byte protocol is used to read a single byte of data from a RAM or EEPROM location whose address has previously been set by a send byte or write byte/word operation. This is illustrated in Figure 9g. 1 2 3 A 4 DA TA 5 A 6 P SLA VE R S AD DRE SS Figure 9e. Single Byte Write To EEPROM Block Write In this operation the master device writes a block of data to a slave device. The start address for a block write must previously have been set. In the case of the ADM1060 this is done by a Send Byte operation to set a RAM address or a Write Byte/Word operation to set an EEPROM address. 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code that tells the slave device to expect a block write. The ADM1060 command code for a block write is FCh (11111100). 5. The slave asserts ACK on SDA. 6. The master sends a data byte that tells the slave device how many data bytes will be sent. The SMBus specification allows a maximum of 32 data bytes to be sent in a block write. 7. The slave asserts ACK on SDA. 8. The master sends N data bytes. Figure 9g. Single Byte Read From EEPROM Or RAM Block Read In this operation the master device reads a block of data from a slave device. The start address for a block read must previously have been set. In the case of the ADM1060 this is done by a Send Byte operation to set a RAM address, or a Write Byte/Word operation to set an EEPROM address. The block read operation itself consists of a Send Byte operation that sends a block read command to the slave, immediately followed by a repeated start and a read operation that reads out multiple data bytes, as follows: 1.The master device asserts a START condition on SDA. 2.The master sends the 7-bit slave address followed by the write bit (low). 3.The addressed slave device asserts ACK on SDA. 4.The master sends a command code that tells the slave device to expect a block read. The ADM1060 command code for a block read is FDh (11111101). -41- 9. The slave asserts ACK on SDA after each data byte. 10. The master asserts a STOP condition on SDA to end the transaction. 1 S 2 3 4 5 6 7 8 9 10 SLAVE COMMAND FCh BYTE WA A A DATA 1 A DATA 2 A DATA N A P ADDRESS (BLOCK WRITE) COUNT Figure 9f. Block Write To EEPROM Or RAM REV. PrJ 11/02 PRELIMINARY TECHNICAL DATA ADM1060 5. The slave asserts ACK on SDA. 6. The master asserts a repeat start condition on SDA. 7. The master sends the 7-bit slave address followed by the read bit (high). 8. The slave asserts ACK on SDA. 9. The ADM1060 sends a byte count data byte that tells the master how many data bytes to expect. The ADM1060 will always return 32 data bytes (20h), which is the maximum allowed by the SMBus 1.1 specification. 10. The master asserts ACK on SDA. 11. The master receives 32 data bytes. 12. The master asserts ACK on SDA after each data byte. 13. The master asserts a STOP condition on SDA to end the transaction. 1 S 2 3 4 56 7 8 9 10 11 12 S LA VE WA A DD RE S S CO MM AN D F Dh B Y TE S LA VE AS RA A D ATA 1 A (B LO CK R EA D ) CO U N T A DD RE SS 13 14 DA T A 32 AP PROGRAMMING ADM1060 Figure 9h. Block Read From EEPROM or RAM ERROR CORRECTION The ADM1060 provides the option of issuing a PEC (Packet Error Correction) byte after a write to RAM, a write to EEPROM, a block write to RAM/EEPROM or a block read from RAM/EEPROM. This enables the user to verify that the data received by or sent from the ADM1060 is correct. The PEC byte is an optional byte sent after that last data byte has been written to or read from the ADM1060. The protocol is as follows:1. The ADM1060 issues a PEC byte to the master. The master should check the PEC byte and issue another block read if the PEC byte is incorrect. 2. A NACK is generated after the PEC byte to signal the end of the read. Note: The PEC byte is calculated using CRC-8. The Frame Check Sequence (FCS) conforms to CRC-8 by the polynomial:C(x) = x8 + x2 + x1 + 1 Consult SMBus 1.1 specification for more information. An example of a block read with the optional PEC byte is shown in figure 9i below. 1 S 2 3 4 56 7 8 9 10 11 12 C O MM AN D F Dh BY TE S LA VE SL AV E AS RA A D AT A 1 A WA (BL OC K RE AD ) C O UN T A DD RE S S AD DR ES S 13 DAT A 32 A 14 15 P PE C A Figure 9i. Block Read From EEPROM or RAM with PEC -42- REV. PrJ 11/02 PRELIMINARY TECHNICAL DATA ADM1060 +5V_IN +5VSB_IN +5V_OUT +5VSB_OUT +3.3V_OUT +3.3VSB_OUT +3.3V_IN +3.3VSB_IN 0.1 F 0.1 F VDDCAP +12V_IN VH VCCP VP1 VP2 VP3 VP4 PDO1 PDO2 PDO3 VB1 -5V_IN VB2 GPI1 GPI2 GPI3 PWRGD VIN VOUT WDI GPI4 ADM1060 PDO4 PDO5 PDO6 PDO7 PDO8 PDO9 R E S E T P W R G O O D VIN_I/O PWR_OK LDO A0 0.9V_OUT +3.3V VIN A1 SCL SDA EN +1.8V VOUT ACK CLKOUT VIN_CORE LDO P EN VIN VOUT -5V_OUT LDO Figure 10. ADM1060 Application Diagram REV. PrJ 11/02 -43- ADM1060 ADM1060 Register Map BLOCK PLB1 PLB2 PLB3 PLB4 PLB5 PLB6 PLB7 PLB8 PLB9 0 1 2 3 4 5 6 7 8 0 P1PLBPOLA P2PLBPOLA P3PLBPOLA P4PLBPOLA P5PLBPOLA P6PLBPOLA P7PLBPOLA P8PLBPOLA P9PLBPOLA UPDCFG 1 P1PLBIMKA P2PLBIMKA P3PLBIMKA P4PLBIMKA P5PLBIMKA P6PLBIMKA P7PLBIMKA P8PLBIMKA P9PLBIMKA PDEN 2 P1SFDPOLA P2SFDPOLA P3SFDPOLA P4SFDPOLA P5SFDPOLA P6SFDPOLA P7SFDPOLA P8SFDPOLA P9SFDPOLA 3 P1SFDIMKA P2SFDIMKA P3SFDIMKA P4SFDIMKA P5SFDIMKA P6SFDIMKA P7SFDIMKA P8SFDIMKA P9SFDIMKA MANID 4 P1GPIPOL P2GPIPOL P3GPIPOL P4GPIPOL P5GPIPOL P6GPIPOL P7GPIPOL P8GPIPOL P9GPIPOL DEVID 5 P1GPIIMK P2GPIIMK P3GPIIMK P4GPIIMK P5GPIIMK P6GPIIMK P7GPIIMK P8GPIIMK P9GPIIMK REVID 6 P1WDICFG P2WDICFG P3WDICFG P4WDICFG P5WDICFG P6WDICFG P7WDICFG P8WDICFG P9WDICFG MARK1 7 P1EN P2EN P3EN P4EN P5EN P6EN P7EN P8EN P9EN MARK2 8 P1PLBPOLB P2PLBPOLB P3PLBPOLB P4PLBPOLB P5PLBPOLB P6PLBPOLB P7PLBPOLB P8PLBPOLB P9PLBPOLB GPI1CFG 9 P1PLBIMKB P2PLBIMKB P3PLBIMKB P4PLBIMKB P5PLBIMKB P6PLBIMKB P7PLBIMKB P8PLBIMKB P9PLBIMKB GPI2CFG A P1SFDPOLB P2SFDPOLB P3SFDPOLB P4SFDPOLB P5SFDPOLB P6SFDPOLB P7SFDPOLB P8SFDPOLB P9SFDPOLB GPI3CFG B P1SFDIMKB P2SFDIMKB P3SFDIMKB P4SFDIMKB P5SFDIMKB P6SFDIMKB P7SFDIMKB P8SFDIMKB P9SFDIMKB GPI4CFG C P1PDBTIM P2PDBTIM P3PDBTIM P4PDBTIM P5PDBTIM P6PDBTIM P7PDBTIM P8PDBTIM P9PDBTIM WDICFG D P1PDOCFG P2PDOCFG P3PDOCFG P4PDOCFG P5PDOCFG PRELIMINARY TECHNICAL DATA P6PDOCFG P7PDOCFG P8PDOCFG P9PDOCFG ERRMASK1 FLT/STS 9 GPI/WDI BSFD1/2 A E BS1OVTH HSOVTH PS2OVTH PS4OVTH BS1OVHYST HSOVHYST PS2OVHYST PS4OVHYST BS1UVTH HSUVTH PS2UVTH PS4UVTH BS1UVHYST HSUVHYST PS2UVHYST PS4UVHYST BS1SEL HSSEL PS2SEL PS4SEL BS2OVTH PS1OVTH PS3OVTH UVSTAT BS2OVHYST PS1OVHYST PS3OVHYST OVSTAT BS2UVTH PS1UVTH PS3UVTH SFDSTAT BS2UVHYST PS1UVHYST PS3UVHYST GWSTAT BS2SEL PS1SEL PS3SEL LATF1 ERRMASK2 H/PSFD1 B -44- REV. PrJ 11/02 PSFD2/3 C PSFD4/ D FLT/STS LATF2 E F PDOSTAT1 PDOSTAT2 PRELIMINARY TECHNICAL DATA ADM1060 OUTLINE DIMENSIONS Dimensions shown in inches and (mm) 28- Lead TSSOP (RU-28) 0.386 (9.80) 0.378 (9.60) 28 15 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) 1 14 PIN 1 0.006 (0.15) 0.002 (0.05) SEATING PLANE 0.0256 (0.65) 0.0118 (0.30) 0.0075 (0.19) BSC 0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090) 8o 0o 0.028 (0.70) 0.020 (0.50) Revision History Rev. H 1. Update of specs. pages 2. Inclusion of Table of Contents 3. Inclusion of EEPROM download at Power- Up (p.38) 2Rev. G 1. Update of specs. pages (better definition of supply conditions, inclusion of input impedance, better definition of PDO output conditions). 2. Removal of PUEN (pull-up current source on logic inputs) function (See Rev. F-7). Rev. F 1. Update of specs. to reflect 14V drive capability of charge pumped outputs. 2. Correction of features on bipolar SFD's- only 1 range available in negative mode. 3. Better definition of SFD Glitch Filter 4. Completion of register map- addition of table numbers for each register, addition of register map matrix (p.43) 5. Improved definition of all ADM1060 blocks. 6. Definition of fault/status reporting on the ADM1060 7. Addition of Pull- Up/Down current source on logic inputs 8. Corrected version of how SMBus protocol is implemented on the ADM1060. 9. Inclusion of device ID registers (p.37) REV. PrJ 11/02 -45- |
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